JPS614244A - Nanufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form the second wirings without the occurrence of wire breakdown in the vicinities of openings even in a the case the aspect ratio of each opening is high, by forming a conductor film by using a conducting material having fluidity so that the openings in the second insulating film are buried. CONSTITUTION:Al wirings 3a and 3b in the first layer are formed on the surface of a silicon substrate 1. Then, a PSG film 4 is deposited and formed on the entire surface by e.g., a CVD method. Thereafter, openings 4c and 4d reaching the Al wirings 3a and 3b are formed by reactive ion etching. Then, an organic solvent (conducting material) such as alcohol, in which Ag powder, whose diameter is about 300Angstrom , is included, is applied on the entire surface by a spray method and the like. Heat treatment such as baking is performed, and the organic solvent is evaporated. As a result, the Ag powder is deposited in the insides of the openings 4c and 4d and on the PSG film 4. Thus a conductor film 10 is formed. Then two-layer structured wirings 14a and 14b comprising Al films 11a and 11b and conductor films 10a and 10b formed by the Ag powder are formed. Thereafter photoresists 12a and 12b are removed, and a semiconductor device having the two-layer wiring structure of the Al wirings 3a and 3b and the wirings 14a and 14b is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device,
It is most suitable for use in forming multilayer wiring in high-density LSI.

BACKGROUND TECHNOLOGY AND PROBLEMS] Multilayer wiring in S1 has conventionally been formed, for example, by the following method. That is, as shown in FIG. 1, SjO,
A first layer of Ni wiring 3 is formed on the film 2, and then this first layer
After forming PSGSiO2 as an interlayer insulating film so as to cover the ^l structure wA3 of the layer, this PSGSiO2 constant portion is removed by etching to form an opening 4a (contact hole).
form. Note that a taper 4b is formed at one end of the opening 4a.

Next, an Ajl film is deposited on the entire surface, and this AL film is then patterned to form a second layer A/wiring 5 connected to the first layer AN wiring 3 through the opening 4a. . In this way, a two-layer wiring consisting of the Hep wiring 3 and the Af wiring 5 is formed.

However, as a result of the miniaturization of elements as the density of LSI increases, the following problems have arisen.

In other words, miniaturization of elements prevents a decrease in the operating speed of LSI,
There is a limit to scaling in the vertical direction (thickness or depth direction) due to reasons such as preventing a decrease in the amount of charge handled by one transistor and fixing the drive voltage to 5V. 10) This is done by scaling. However, when lateral scaling is performed in this way, the ratio h/d of the depth h to the diameter d of the opening 4a shown in FIG. 1, that is, the so-called aspect ratio (
As a result, the step coverage of the Aff wiring 5 in the second layer deteriorates in the vicinity of the opening 4a, and disconnection of the Aρ wiring 5 is likely to occur. In order to prevent this, conventionally, a taper 4b is formed at the upper end of the opening 4a as shown in FIG. 1 to improve the step coverage of the AFi wiring 5 in the vicinity of the opening 4a. However, in such a method, firstly, when the aspect ratio becomes large (especially when it is 0.5 or more), the step coverage of the β wiring 5 becomes awkward as shown in FIG. Help It is difficult to avoid disconnection of wiring 5. Secondly, the opening 4a has a taper 4b.
When trying to obtain good step coverage by forming a
The horizontal and vertical dimensions t and t' of b are the diameter d of the opening 4a.
and must be larger than the depth h, so L
Not suitable for high density SI. Third, as shown in FIG. 4, the PSG film 4 has different thicknesses β
An opening 4c that reaches the wirings 3a and 3b.

When forming 4d at the same time by etching 1. The diameter of the opening 4d with the smaller depth becomes considerably larger than that in the case where the taper 4b is not formed.

For example, as a technique for solving the same problem as mentioned above in the field of circuit boards, etc., there is
JP-A-55-108103 and JP-A-56-134404 disclose a method of connecting contact holes using a liquid conductive material, and JP-A-55-108103 and JP-A-56-134404 disclose a liquid conductive material based on gallium. ing.

Purpose of the Invention In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that corrects the above-mentioned drawbacks of the conventional method for manufacturing a semiconductor device for forming multilayer wiring. .

Summary of the Invention A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a first interconnect on a first insulating film; forming an opening in the second insulating film that reaches the first wiring; a step of assimilating the fluid conductive material to form a fluid conductive material, and a second step connected to the solidified conductive material; and a step of forming the second wiring on the second insulating element. By doing this, even if the second insulating film has a large open F7 aspect ratio, the second wiring can be formed without causing disconnection of the wiring in the vicinity of the opening.

EXAMPLE Hereinafter, an example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

As shown in FIG. 5Δ, the silicon substrate 1
A SiO2 film 2 (first layer insulating film) is formed on the surface.

5 This Sin, the thicker part and the smaller part on the back of the film 2 constitute the field oxide film 2a and, for example, the gate oxide film 2b, respectively, and these field oxide film 2a and gate oxide film 2b A step 2c is formed between them. Next, an AA film is deposited on the 5402 film 2 by, for example, sputtering, and then this AI! A predetermined portion of the film is etched and removed to form first layer Aβ wirings 3a and 3b. Next, PSG is applied to the entire surface by, for example, CVD;
Film 4 is deposited and the surface of PSGI+94 is then planarized by a known planarization process as shown in FIG. 5A. Thereafter, a predetermined portion of the PSG film 4 is etched away by reactive ion etching (RIF) to form an opening 4c that reaches the ρ wirings 3a, 3 and b.

Form 4d. Note that as a result of the surface of the PSGllu4 being flattened as described above, the depths of the openings 4c and 4d are different from each other, with the opening 4c being deeper than the opening 4d. Further, in the silicon substrate 1, a predetermined diffusion layer (for example, M
In the OS LSI, a source region, a drain region, etc.) are formed in the OS LSI, but their illustration is omitted in FIG. 5A (the same applies hereinafter).

Next, as shown in Figure 5B, an organic solvent (conductive substance) such as alcohol mixed with Ag powder having a particle size of about 300 particles is applied to the entire surface by spraying (mist or shower). 41, and then heat treatment such as baking is performed to evaporate the organic solvent. As a result, as shown in FIG.
The Ag powder is deposited on the G film 40. In this way, the openings 4c and 4d of the PsG film 4 are filled with Ag powder. Note that the film made of the above-mentioned Ag powder is hereinafter referred to as a conductive film 10.

Next, as shown in FIG. 5D, a β film II (or an 8β-4Si alloy film, etc.) is deposited on the entire surface by sputtering (or vacuum evaporation), and then photo is deposited on this film 11. After coating resist 12, this photoresist 1
2 into a predetermined shape by patterning the photoresist 12.
a, 121). Next, using these photoresists 12a and 12b as a mask, for example, RI similar to that described above is performed.
By sequentially etching the ^l film 11 and the conductive film 10 using E, two-layer structure wirings 14a and 14b consisting of the ^l films 11a and llb and conductive films 10a and 10b made of Ag powder are formed. After this, Photoregis)
122.12b is removed to complete a semiconductor device with a two-layer wiring structure of Aj2 wirings 3a and 3b and wirings 14a and 14b.

According to the embodiment described above, in the step shown in FIG. 5B,
By applying an organic solvent mixed with Ag powder to the entire surface and then performing heat treatment to evaporate the organic solvent, A
Since the conductive film 10 is formed of g powder, there are the following advantages. That is, PSGSnO2[214c,4
These openings 4c are completely filled with the conductive film 1o.

Even if the aspect ratio of the openings 4d is, for example, 0.5 or more, the AZ films 11a, I
lb step cover 1/soji is getting worse l membrane ti
a, zb, hence the wiring 14a.

14b will not be disconnected. Also, ^β membrane 11a,
This is advantageous in forming a multilayer wiring because no recess is formed in the portion of llb that is opposite J+6 to the openings 4c and 4d. Similarly, since there is no need to provide tapers at the upper ends of the openings 4c and jd as in the prior art in order to prevent wire breakage, there is also the advantage that the manufacturing process is relatively simple.

Furthermore, since there is no need to provide a taper in the openings 4c and 4d as described above, even though the depths of these openings rII7Ic and 4d are different from each other, as described in connection with FIG. It is possible to solve the problem that the diameter of the opening 4d becomes larger than the diameter of the opening 4C by etching to form a taper. Therefore, by repeating the same steps as in the two series of embodiments, it is possible to form a multilayer wiring having two or more layers.

Furthermore, according to the embodiment described above, even if the openings 04c and 4d are not tapered, the ^p film 1 is not formed in the vicinity of the openings 4c and 4d.
Since disconnection of wires 1a and llb does not occur, the distance between the openings 4c and 4d can be reduced, which is extremely advantageous in increasing the density of LSI.

The present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention. For example, in the above-mentioned example, a solvent mixed with Ag powder was used as a fluid conductive substance, but
Instead of an organic solvent, an organic adhesive with fluidity such as an epoxy resin may be used, and instead of Ag powder,
4 types of metal powders such as AI C1Cu mixed together at the same time! ! A solvent or an organic adhesive may also be used. For example, if an organic adhesive mixed with metal powder is used, even if it is an insulator at the time of application, it may be necessary to heat the adhesive afterwards or locally apply energy to the applied film using a laser beam, etc. conductivity can be imparted by Further, as the conductive substance having fluidity, it is also possible to use a metal that has been softened by processing such as heating.

Note that the conductive material used in the above embodiments is LSI
Used as wiring material for ^j! , Mo, Ti
, W, Pt, metals such as Au, alloys of these metals,
The contact resistance between these metals and silicon compounds (metal silicides) and silicon, etc. is from several hundred ohms to several ohms (expressed in area resistivity: 10-4 to S0 cm"), and the base material is It is preferable to make ohmic contact with the material. Note that heat treatment may be performed as necessary to reduce contact resistance or make ohmic contact.

In addition, the above-mentioned conductive substances include various wiring materials as mentioned above,
1. SiO2,5IJ4 used in
It is preferable that the adhesive has high adhesion to an insulating material such as an organic insulating material. Note that heat treatment may be performed as necessary to improve adhesion.

Further, the conductive substance can be used as a wiring material, a semiconductor, and an electrically conductive material at room temperature or at a temperature used for the heat treatment.
! ! II″″′″1°'4B$5jje;t”MC
It is preferable that I-k '14'' 1 line and insulation breakdown etc. not occur.

Furthermore, in the above embodiments, the organic solvent mixed with A[i powder was applied by spraying, but other methods such as spin coating may be used if necessary.

Further, in the above embodiment, the conductive film 10 was formed on the entire surface as shown in FIG. 5C, and then the An film 11 was formed, but the following method may be used. That is, after forming the conductive film 10, this conductive film 10 is etched by RIE to form the sixth
After setting the state shown in Figure A, as shown in Figure 6B, the fifth
Similarly to Figure D, the film 11 and photoresist 12a, 1
2b is formed, and then, as shown in FIG.
'F, etching to the second layer wiring 5a, 5.
b may also be formed.

Furthermore, in the above embodiment, PSGSiO4lTl4
A conductive substance was formed throughout the interior of c and 4d, but
For example, as shown in FIG. 7, an opening 4c.

Even if a conductive material is formed only at the bottom of the openings 4d, the depths of the openings 4c and 4d are effectively reduced, resulting in a smaller aspect ratio.
This can prevent disconnection of the wirings 14a and 14b (not shown) that run near the wire 4d.

In the above embodiment, the PSGSiO4 surface was flattened into LIi in the step shown in FIG. 5A, but this flattening is not necessarily necessary and can be omitted if necessary.

Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, in particular, since the conductive material having fluidity is formed so as to fill at least the opening 1 in the second insulating film, the aspect ratio of the opening can be reduced. Even when the second wiring is high, the second wiring can be formed in the vicinity of the opening without causing disconnection of the wiring.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing the shape of the wiring near the opening of the glabella insulating film in a conventional semiconductor device, and FIG. 3 shows a large taper at the upper end of the opening of the interlayer insulation Jlu in the conventional semiconductor device. FIG. 4 is a cross-sectional view showing a state in which openings are formed in the glabella insulating film in a conventional semiconductor device, and FIG.
5E to 5E are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIGS. 6A to 6C are 5C to 5E for explaining the present invention in detail. FIG. 7 is a sectional view similar to FIG. 5C showing a different modification of the modified side stop shown in FIGS. 6A to 6C. In addition, in the symbols used in the drawings, 2--1----------5iO,z film (first insulating film) 2 cm knee--1--1 step difference 3, 3a, 3b- -----＾#1mc! line (first
wiring) 4-------------P S G film (
second insulating film) 4a, 4c, 4d---
One opening 5--------------------- A 4 wiring 5a+
5b ---- to l wiring (second wiring) 10---
-------1 conductive film (solidified conductive substance) 11a
, llb---A 12 membranes 14a, 14h---
- wiring (second wiring).

Claims (1)

[Claims] forming a first wiring on the first insulating film; forming a second insulating film covering the first wiring and the first insulating film; and forming a second insulating film on the second insulating film. forming an opening reaching the first wiring; and at least the step of forming an opening reaching the first wiring;
a step of forming a fluid conductive material so as to fill the opening in the insulating film; a step of solidifying the fluid conductive material; and a step of being connected to the solidified conductive material. and forming a second wiring on the second insulating film.