JPS6145382B2 - - Google Patents

Info

Publication number
JPS6145382B2
JPS6145382B2 JP56014471A JP1447181A JPS6145382B2 JP S6145382 B2 JPS6145382 B2 JP S6145382B2 JP 56014471 A JP56014471 A JP 56014471A JP 1447181 A JP1447181 A JP 1447181A JP S6145382 B2 JPS6145382 B2 JP S6145382B2
Authority
JP
Japan
Prior art keywords
layer
silicon
trench
isolation region
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56014471A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56137651A (en
Inventor
Uenkataraman Tarishunamaa
Hon Yun Bobu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS56137651A publication Critical patent/JPS56137651A/ja
Publication of JPS6145382B2 publication Critical patent/JPS6145382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
JP1447181A 1980-03-17 1981-02-04 Method of forming exfoliating region Granted JPS56137651A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/130,882 US4274909A (en) 1980-03-17 1980-03-17 Method for forming ultra fine deep dielectric isolation

Publications (2)

Publication Number Publication Date
JPS56137651A JPS56137651A (en) 1981-10-27
JPS6145382B2 true JPS6145382B2 (2) 1986-10-07

Family

ID=22446794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1447181A Granted JPS56137651A (en) 1980-03-17 1981-02-04 Method of forming exfoliating region

Country Status (4)

Country Link
US (1) US4274909A (2)
EP (1) EP0036111B1 (2)
JP (1) JPS56137651A (2)
DE (1) DE3177048D1 (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0568822U (ja) * 1991-11-11 1993-09-17 株式会社日本ばし大増 弁当箱包装用の紙ケース

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
US4325182A (en) * 1980-08-25 1982-04-20 General Electric Company Fast isolation diffusion
JPS5864044A (ja) * 1981-10-14 1983-04-16 Toshiba Corp 半導体装置の製造方法
US4390393A (en) * 1981-11-12 1983-06-28 General Electric Company Method of forming an isolation trench in a semiconductor substrate
JPS58100441A (ja) * 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法
NL8105559A (nl) * 1981-12-10 1983-07-01 Philips Nv Werkwijze voor het aanbrengen van een smalle groef in een substraatgebied, in het bijzonder een halfgeleidersubstraatgebied.
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
JPS5935445A (ja) * 1982-08-24 1984-02-27 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US4444605A (en) * 1982-08-27 1984-04-24 Texas Instruments Incorporated Planar field oxide for semiconductor devices
JPS5978542A (ja) * 1982-10-27 1984-05-07 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
DE3242113A1 (de) * 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper
JPS60207339A (ja) * 1984-03-30 1985-10-18 Matsushita Electronics Corp パタ−ン形成方法
NL8402859A (nl) * 1984-09-18 1986-04-16 Philips Nv Werkwijze voor het vervaardigen van submicrongroeven in bijvoorbeeld halfgeleidermateriaal en met deze werkwijze verkregen inrichtingen.
US4982262A (en) * 1985-01-15 1991-01-01 At&T Bell Laboratories Inverted groove isolation technique for merging dielectrically isolated semiconductor devices
JPS61198780A (ja) * 1985-02-28 1986-09-03 Toshiba Corp 半導体装置の製造方法
US4753901A (en) * 1985-11-15 1988-06-28 Ncr Corporation Two mask technique for planarized trench oxide isolation of integrated devices
US4654119A (en) * 1985-11-18 1987-03-31 International Business Machines Corporation Method for making submicron mask openings using sidewall and lift-off techniques
US4826781A (en) * 1986-03-04 1989-05-02 Seiko Epson Corporation Semiconductor device and method of preparation
JPS6318673A (ja) * 1986-07-11 1988-01-26 Yamaha Corp 半導体装置の製法
JPS6377122A (ja) * 1986-09-19 1988-04-07 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
FR2610141B1 (fr) * 1987-01-26 1990-01-19 Commissariat Energie Atomique Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit
JPH0727974B2 (ja) * 1988-04-26 1995-03-29 三菱電機株式会社 半導体記憶装置の製造方法
US5008210A (en) * 1989-02-07 1991-04-16 Hewlett-Packard Company Process of making a bipolar transistor with a trench-isolated emitter
JP2870054B2 (ja) * 1989-10-25 1999-03-10 ソニー株式会社 半導体装置の製造方法
US5124775A (en) * 1990-07-23 1992-06-23 National Semiconductor Corporation Semiconductor device with oxide sidewall
KR0120572B1 (ko) * 1994-05-04 1997-10-20 김주용 반도체 소자 및 그 제조방법
US5426059A (en) * 1994-05-26 1995-06-20 Queyssac; Daniel G. Method of making vertically stacked bipolar semiconductor structure
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
WO1997038442A1 (en) * 1996-04-10 1997-10-16 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US5929368A (en) * 1996-12-09 1999-07-27 The Ensign-Bickford Company Hybrid electronic detonator delay circuit assembly
SE519975C2 (sv) * 1999-06-23 2003-05-06 Ericsson Telefon Ab L M Halvledarstruktur för högspänningshalvledarkomponenter
EP1161769A1 (en) * 1999-12-24 2001-12-12 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer
DE102004034572B4 (de) 2004-07-17 2008-02-28 Infineon Technologies Ag Verfahren zum Herstellen einer Struktur auf der Oberfläche eines Substrats
US20070001267A1 (en) * 2004-11-22 2007-01-04 Farrokh Ayazi Methods of forming oxide masks with submicron openings and microstructures formed thereby
US20080001213A1 (en) * 2006-06-29 2008-01-03 International Business Machines Corporation Structures and methods for manufacturing high density narrow width mosfets
KR100822592B1 (ko) * 2007-03-23 2008-04-16 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
US8084347B2 (en) * 2008-12-31 2011-12-27 Sandisk 3D Llc Resist feature and removable spacer pitch doubling patterning method for pillar structures
US8114765B2 (en) 2008-12-31 2012-02-14 Sandisk 3D Llc Methods for increased array feature density
US11887945B2 (en) * 2020-09-30 2024-01-30 Wolfspeed, Inc. Semiconductor device with isolation and/or protection structures
EP4290555A1 (en) * 2022-04-24 2023-12-13 Changxin Memory Technologies, Inc. Manufacturing method for semiconductor structure, and structure thereof

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
US3725160A (en) * 1970-12-30 1973-04-03 Texas Instruments Inc High density integrated circuits
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3979237A (en) * 1972-04-24 1976-09-07 Harris Corporation Device isolation in integrated circuits
US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
US3956033A (en) * 1974-01-03 1976-05-11 Motorola, Inc. Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector
US3969168A (en) * 1974-02-28 1976-07-13 Motorola, Inc. Method for filling grooves and moats used on semiconductor devices
US3892608A (en) * 1974-02-28 1975-07-01 Motorola Inc Method for filling grooves and moats used on semiconductor devices
US3979765A (en) * 1974-03-07 1976-09-07 Signetics Corporation Silicon gate MOS device and method
JPS5131186A (2) * 1974-09-11 1976-03-17 Hitachi Ltd
JPS5146083A (en) * 1974-10-18 1976-04-20 Hitachi Ltd Handotaisochino seizohoho
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
US3920483A (en) * 1974-11-25 1975-11-18 Ibm Method of ion implantation through a photoresist mask
US4037307A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
GB1527894A (en) * 1975-10-15 1978-10-11 Mullard Ltd Methods of manufacturing electronic devices
GB1535086A (en) * 1976-03-22 1978-12-06 Western Electric Co Manufacture of transistors
US4093503A (en) * 1977-03-07 1978-06-06 International Business Machines Corporation Method for fabricating ultra-narrow metallic lines
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
JPS5789226A (en) * 1980-11-19 1982-06-03 Ibm Method of etching silicon nitride layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0568822U (ja) * 1991-11-11 1993-09-17 株式会社日本ばし大増 弁当箱包装用の紙ケース

Also Published As

Publication number Publication date
EP0036111B1 (en) 1989-05-03
US4274909A (en) 1981-06-23
JPS56137651A (en) 1981-10-27
EP0036111A2 (en) 1981-09-23
EP0036111A3 (en) 1986-01-02
DE3177048D1 (en) 1989-06-08

Similar Documents

Publication Publication Date Title
JPS6145382B2 (2)
US4502913A (en) Total dielectric isolation for integrated circuits
US4546536A (en) Fabrication methods for high performance lateral bipolar transistors
US4771328A (en) Semiconductor device and process
JP2554831B2 (ja) 基板分離トレンチを形成するための半導体処理方法
US4583106A (en) Fabrication methods for high performance lateral bipolar transistors
EP0100897B1 (en) Method for contacting a pn junction region
US4044452A (en) Process for making field effect and bipolar transistors on the same semiconductor chip
EP0137905B1 (en) Method for making lateral bipolar transistors
EP0552671A2 (en) Isolation technique for silicon germanium devices
EP0062170B1 (en) Process for forming self-aligned dielectric isolation
US5963822A (en) Method of forming selective epitaxial film
US4661832A (en) Total dielectric isolation for integrated circuits
JPS59124141A (ja) 半導体装置の製造方法
JPH0793315B2 (ja) 半導体装置およびその製造方法
US4900689A (en) Method of fabrication of isolated islands for complementary bipolar devices
JPH05129319A (ja) エピタキシヤル・ベース領域を持つたトランジスタ構造とその作製方法
EP0144762B1 (en) Methods for forming closely spaced openings and for making contacts to semiconductor device surfaces
US3997378A (en) Method of manufacturing a semiconductor device utilizing monocrystalline-polycrystalline growth
US6255184B1 (en) Fabrication process for a three dimensional trench emitter bipolar transistor
US5763931A (en) Semiconductor device with SOI structure and fabrication method thereof
US6445043B1 (en) Isolated regions in an integrated circuit
US4026736A (en) Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor
US4696095A (en) Process for isolation using self-aligned diffusion process
US6774455B2 (en) Semiconductor device with a collector contact in a depressed well-region