JPS6149286A - Video signal processing device - Google Patents

Abstract

PURPOSE:To enable to precisely generate a reference signal by obtaining a multivalued signal including the binary signal of a digital video signal compared with the reference signal. CONSTITUTION:A digital video signal V1 outputted from an A/D converter 1 is supplied to ROM as a comparing means outputting a multivalued signal V0 by comparing the reference signal of a reference signal generating part 2 with a digital video signal. The reference signal generating part 2 has a function to generate a reference signal Vr which changes following a digital video signal V1, and is composed of ROM4, 7 and 10, a latch 5, an AND gate 6, a counter 8 and an invertor 9. A digital video signal Vi and an output signal Vr1 which is made clear by the later explanation are given to ROM4, and the reference signal Vr is outputted by ROM3 as shown in the right formula under the following relational expression based upon the relation of the size of the digital video signal Vi and the output signal Vr1.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a video signal processing device that converts an analog video signal obtained by scanning with an optical character reading device or the like into a binary signal corresponding to a white level and a black level. (Prior art) Conventionally, in optical character reading devices, for example, the fifth
As shown in the figure, characters drawn on a sheet of paper are illuminated by a light source 22, and the reflected light from this illumination is incident on the image scanner barrel through a mirror and photoelectrically converted by line scanning by the image scanner. The digital video signal is then binarized in the signal processing circuit 5 according to the white level and black level.The digital video signal is then subjected to signal processing, and optically read characters are generated based on this binarized data. I am asking people to be aware of this. By the way, as shown in Figure 6 (11), the analog video signal obtained from the image scanner Sae is a bright signal in the center due to the influence of the light source and lens1.This phenomenon is usually known as shape pufferfish, and this Even after correcting the shading, variations in brightness remain in the analog video signal, as shown in Figure 8146), and accurate signal processing cannot be performed by binarization based on comparison with a fixed reference level. Therefore, in order to create a reference signal that follows changes in the analog video signal, a peak hold circuit shown in FIG. 7 is used for signal processing. In the peak hold circuit shown in FIG. 7, a capacitor C1 for signal holding is provided between the buffer amplifier 26 and n, and the capacitor C5 is rapidly charged by a diode D. On the other hand, the waste paper of the capacitor C acts as a resistor. By doing so, the discharge is gradual. In other words, the peak hold circuit has the characteristic of following the white part of the background with a photoelectric discharge with a fast time constant, and following the dotted part corresponding to the character with a discharge with a fast time constant, as shown by the broken line in Figure 8. Obtain the peak hold output. The output of this peak hold circuit is divided to a specified signal level by a resistor R3, and a reference level vctta that follows changes in the analog video signal is set to a comparator 4.
The comparator 4 obtains a binary output v0 which is, for example, an L level in a white portion and an H level in a dotted portion by comparison with an analog video signal. (Problem to be solved by the invention) However, in such conventional analog signal processing, the charge/discharge characteristics of the peak hold circuit that creates the reference value are determined by diodes, capacitors, and resistors, so each In order to correct variations in the elements, voltage adjustment had to be carried out using a number of adjustment means such as polyurethane, -me, etc., and it was also necessary to compensate for changes in temperature and other characteristics peculiar to analog. Furthermore, due to paper surface noise, fluctuations in image scanner sensitivity, variations in the light source light intensity distribution, etc., the charging time constant of the peak hold circuit must be made faster in order to track the white area. There is a problem that there are limitations, and when it becomes necessary to change the video frequency, the time constant of the peak hold circuit must be readjusted. (Means for Solving the Problems) The present invention has been made in the haste to solve the problems of the conventional art, and provides proper binarization that follows analog video signals without requiring any circuits. In order to be able to generate a reference signal, the analog video signal tube is converted into a digital signal using an A/DzR framer, and the fi semi-multiplying signal generating means is stored in advance with multiple reference values, and the A/D* converter is used to generate a reference signal. The digital output value is compared with the previously output reference value, and when the digital value is greater than or equal to the previous reference value, the stored reference value corresponding to the digital value is output as a new reference value; When BA is smaller than A, K retains the memory output of the previous reference value, and decreases the reference value step by step every time a certain period of time elapses, so that the reference value from such reference value generation means and The digital video signal is compared with the digital output of the λ/D converter by a comparing means, and the digital video signal is converted into a multi-valued signal which is more than a binary signal. (Embodiment) FIG. 1 is a circuit block diagram showing an embodiment of the present invention. First, to explain the configuration, l is an A/D converter that converts an analog video signal obtained by an image scanner into a digital video Vi, and the digital video signal vI output from the A/D converter l is a reference signal. A multilevel signal v is generated by comparing the generator 2, the reference key signal, and the digital video signal.
It is supplied to RO.M3 as a comparison means which outputs o. The reference signal generator 2 has a function of generating a reference signal Vrt that changes in accordance with the digital video signal V+, and
, 7, 10, a latch 5, an AND gate 6, a counter 8, and an inverter 9. Each circuit element in this reference signal generating section 2 will be explained as follows. The digital video signal Vi and the output signal Vrt of the ROM 7, which will be explained later, are given to the ON+4, and based on the magnitude relationship between the digital video signal v1 and the output signal Vr1, a reference is made under the following relational expression. Signal V "O OM 3"
Output to. That is, when the digital video signal V+1 is greater than or equal to the output signal Vrx of the ROM 7, the digital video coefficient vI is output as the reference 1M coefficient V, and on the other hand, the digital video signal 1 v1 is smaller than the output signal Vrt of the ROM 7. Time, reference signal■
The reference signal Vr based on the comparison between the digital video signal Vt and the output signal Vr1 in the OM 4 is outputted as the output signal Vrl. ROM4 table memory with table address data
This can be achieved by memorizing the . That is, a memory table is created with each digital bit of the signals V+ and Vrl as an address, and a specific V

[Write the value of Vl or Vr1 determined from the magnitude relationship of equation (1) above into the data area of the table position determined by the value of [ and VrL], and specify the data position of the table memory using Vr and Vrl as address data. In other words, in the ROM 4, a plurality of reference signals V used for comparison with the digital video signal v1 are stored in advance in the ROM 4. Also, ROM4 is MSB
The MSB bit outputs a 1cMsB pit as follows based on the magnitude relationship between the digital video signal Vt and the output signal "/r1" of the ROM 7. Next, the latch 5 outputs the MSB of fL OM4. It has a function of latching the previous reference signal Vr given to the ROM 3 based on the bit output in order to generate the next reference signal.That is, the latch control of the latch 5 is performed by the output of the AND gate 6, and The gate 6 is given the MSB bit output of R○1 to 14 and the same clock pulse Ci as the A/Dim clock pulse used in the A/Dim device 1, and the MSB bits are "1". The H level output when v1≧vrx, that is, the reference signal Vr for OAi 3 when v1≧vrx
is latched and output as a latch signal Vr2. on the other hand,
The MS13 bit becomes 0". When V + (Vr > Note that launch 5 is cleared every time a horizontal synchronizing signal is obtained.
Multiply by coefficient β determined by l0 Vr1 = β・Vrz ・・・・・・・・・・・・
・・・・・・・・・・・・・・・Signal Vr determined by (3)
Generates 1. Here, the value of the coefficient β according to equation (3) is determined by the output of the counter OM 10 from the counter 8. First, the counter 8 is connected to the memory of the ROM 4 via the inverter 9.
SB bit output is given, and when N18B=O1, that is, right<111, the counter 8 performs a clock pulse CK o counting operation with the H level output of the inverter 9.
Give count output to l0. The ROM 10 outputs the output 00.01.10.11 every time the output of the counter 8 reaches a predetermined value. ...... A memory output is generated, and R is generated according to the memory output of ROM10.
The value of the coefficient β of the equation (3) in OM7 is determined. For example, the values of coefficient β of R and 0M7 for the output of ROM10 are predetermined as shown in Table 1 below. Table-1 On the other hand, 1sB from ROM 4 to M8B pit =
1, that is, when v1≧Vr1, the output of the inverter 9 becomes L level, and the counter 8 is cleared, and at this time, the RO
The storage output of ~110 is fixed to OO, therefore, the value of the coefficient β of the equation (3) at 17 is fixed to β=], and the latch output Vr2 is directly used as the output signal Vr1.
It is supplied to ROM 4 as Furthermore, the RO 13, which operates as a comparison means inputting the digital video signal V+ from the A/Df converter 1 and the reference signal Vr, records table data given, for example, in a missing form.
Performs lazy output. Vr-V"・・・・・・・・・・・・
...(4)■・"Vr" This equation (4) means that, for example, if v1≧Vr, where the digital video signal Vi is greater than or equal to the reference signal Vr, Vo=O is output, On the other hand, if the digital video signal vI is smaller than V (Vr), then v
A signal having a value corresponding to the ratio of I and Vr, for example, vo=1 to 15, is output at a multilevel level. That is, it is possible to output the signal v0 at a multilevel level depending on how low or dark the digital video signal v1 is with respect to the reference signal Vr. Incidentally, the coefficient X in the above equation (4) can be set to an arbitrary value, and v is expressed at a multi-value level. It can be set as appropriate depending on the signal expression method. Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to the signal waveform diagram shown in FIG. First, following the horizontal synchronizing signal, an analog video signal obtained by an image scanner is input to the λ/D converter 1, and is converted into a digital video signal Vt1Cffi as shown in an enlarged view of part A of the analog video signal. On the other hand, the latch 5 is initially cleared by the horizontal synchronization signal, and since this clearing of the latch 5 makes Vr2=0, the ROM 7 outputs a signal Vrl having a predetermined digital level as an initial value, for example, Vrt =40 is output. Assuming that the digital level of the digital video signal VI obtained first is V+=50, the digital video signal Vi is compared with the initially set signal Vr1 in the OM4, and the condition of v1≧Vrl is satisfied. As is clear from the above equation (1), the ROM 4 outputs the reference signal Vr=50, which is equal to the digital video signal vI, to the OM 3. Therefore, the ROM 3 generates an output such that Vo=O since the value of equation (4) is negative. On the other hand, the M S B bit output from the OM4 is M
Since S B = l, Vr = 50 is latched in the latch 5 by the (level output) of the AND gate 6, and the latch output is changed to Vrz = 50. Furthermore, MSB = 1
Since the output of the inverter 9 is at L level, the counter 8 is cleared, and the output of the ROM 10 is OO, so the coefficient β of FLOM7 is fixed at 1.
The output signal Vr1 of R, OM 7 is the initialized Vrx.
=40 to vrl=50. Next, the digital level of the digital video signal v1 is vi=
Assuming that V+=40 changes from so, at this time Vr1=
Since it is FiJ, it becomes Vi (Vr), and the above (1)
As is clear from the equation, vr1=(capital) is outputted to the ROM3 as a reference signal V.
A multilevel output vo is generated. On the other hand, when Vl=40, the MSB bit of ROM 4 is M8B=0, so the output of AND gate 6 goes to L level, and latch 5 uses the first latched reference signal Vr.
The latch output Vr2 of =50 is held, and the output Vrl of the ROM 7 remains unchanged at Vrl='A. However, the clear state of the counter 8 is released by the h level output of the inverter 9 due to MSB=0, and the counter 8 starts counting clock pulses CK. When a predetermined count number is obtained by the counting operation of the counter 8, the ROM 10 switches from the previous output OO to 01, and as is clear from the above-mentioned clothes-1 (the ROM 1
With the 01 output of 0, the coefficient β in ROM7 changes from β=1 to β
= 0.95, output Vr1 of ROM 7
is given by the above equation (3) Vr1=βVr2=0
, 95 x 50 wheels, the output changes to 47. Furthermore, in the signal waveform diagram of FIG. 2, the changed reference signal V
Since the obtained digital video coding layer is small for r = 47, the latch circuit 5 continues to hold the vrz-leap and the counter 8 continues to count, and each time a predetermined count of 1 is reached, R, Q The output of M 10 changes to 01.10 by 7 terms, and the coefficient β at 几0, 'vi 7 becomes β
= 0.92.0.90, and when a digital video signal smaller than M$1m corresponding to the peak level is detected, this digital video signal does not follow and the reference signal V' changes at regular intervals. It decreases stepwise at a rate based on the coefficient β. As a result, the reference signal V shown by the broken line in FIG. In contrast, it is possible to create a reference signal equivalent to that in the conventional analog system with a tracking delay, and in OM 3, an output representing the low and dark digital video signal Vt with respect to the reference signal Vr in multilevel levels. In the embodiment shown in FIG. 1, the reference signal obtained based on data one bit before is compared with the current video data.
By inputting the reference signal Vr with a delay through a play circuit, it is also possible to perform a comparison operation with a reference signal created based on video data n bits before. FIG. 3 is a circuit block diagram showing another embodiment of the present invention. This embodiment is characterized in that a comparator is used to generate the reference signal. In FIG. 8g3, the A/D converter 1 and ROM 3 are the same as in the embodiment shown in FIG. 1, but the circuit configuration of the reference signal generator 2 is different. That is, when the digital video signal Vi of the A/D converter 1 is input to the latch 11, it is also input to the comparator 12, the latch output Vr2 of the latch 11 is given to the comparator 12, and the output of the comparator 12 is OR gated. 15 to the latch 11 as a latch control signal. This latch 11, comparator 12
The circuit section including the OR gate 15 has a peak hold function of the digital video signal V+. That is, the comparator 12 compares the latch output Vr2 and the digital video Vi, and when 'h≧Vτ2, it produces an H level output, and VI (
When Vrz, the output is L level. As a result, latte 1
A peak hold is performed to latch the current digital video signal V+ only when the current digital video signal V1 is larger than the previous latch output Vr2 which was peak held at 1. In addition, the output of the comparator 12 becomes a signal that controls the counting operation of the counter 8 via the inverter 9, and while the digital video signal v1 is smaller than the peak-held output Vrz of the latch 11, the clock pulse CK of the counter 8 is Perform counting operation. The function of the ROM 10 based on the count output of the counter 8 is the same as that shown in FIG.
1. ...... Give the output to ROM4. The ROM 4 is the same as the embodiment shown in FIG. 1, and multiplies the latch output Vr2 peak-held by the latte 11 by the output of the ROM10 to generate a reference signal such that Vr=βVrz. The reference signal y' from FLOM4 is given to the OM3 and also to the comparator 14, where it is compared with the digital video signal v1.Comparator 14
When the digital video signal Vt exceeds the reference signal V' which decreases in steps with the passage of time based on the counting operation of the counter 8, an output of 1 level is generated, and the OR gate 15
The latch 11 is caused to latch the digital video signal V+ through the latch 11. Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to the signal waveform diagram shown in FIG. 4. First, the latch 11 is initially cleared by the horizontal synchronizing signal, and with this clearing, Vr2=O.
Also set the reference signal Vr from ROM 4 to V'=0. Next, when the first digital video signal is obtained, v'2=0.
0, the comparator 12 always generates an H level output, and the latch 11 latches the first obtained digital video signal v1 as a peak value, and supplies it to RO+%i 4 to create a reference signal that makes Vr=vi. Set to OM 3. As shown in FIG. 4, if a digital video signal V+ exceeding Vr2 peak-held by the latch 11 is sequentially obtained, the comparator 12 generates an H level output each time the digital video signal v1 is obtained, and the latch 11 outputs an H level output. 11 performs peak hold of the digital video signal which increases sequentially, and the reference signal Vr2 from ROM 4 also increases in accordance with this peak hold. Next, if the digital upper No. 1146 V+ falls with respect to the reference signal Vr, the output of the comparator 12 becomes L level, the previous digital video signal Vr is held in the latch 11, and on the other hand, the H level output of the OR gate 9 causes the counter 8 starts the clock pulse CK 'e' @ production,
When a predetermined count of 1 is obtained, the output of RQ M 10 changes to 00, 01, 10, and the ROM 4 sets the coefficient β to 0, 97, 0.95, etc., for example. Switch to 4th
A reference signal vrt- indicated by dotted lines in the figure is generated. If the digital video signal vI exceeds the reference signal V in such a state where the reference signal Vr is generated, the comparator 14 generates an H level output, the latch 11 holds the peak of the new digital video signal V+, and the comparator 14 outputs an H level output. When the output of ROM12 switches to H level, the counter 8 is cleared, and the output of ROM10 returns to 00, and the RO
When the coefficient β of M4 becomes 1, the generation of the reference signal Vr that follows the peak hold of the digital video signal v1 is switched again. As is clear from the signal waveform in FIG. 4, the embodiment shown in FIG. 3 also follows the digital video signal in the white area,
A base IJA signal Vr can be generated that follows the point portion of the digital video signal with a predetermined time delay. Of course, the ROM 3 outputs a signal vO, which is a multi-valued signal that modifies the low level of the digital video signal v1 with respect to the reference signal Vr given by the above-mentioned equation (4), which is the same as in the embodiment shown in FIG. In the embodiment shown in Fig. 1.3, an output with multiple levels is obtained by comparing the digital video signal and the reference signal by the ROM3, but a digital comparator is added to the output of the OM3 to determine the appropriate threshold date. By setting the field level, it is possible to obtain a binary output of an analog video signal. (Effects of the Invention) As described above, according to the present invention, an analog video signal is converted into a digital signal by an A/D converter, a plurality of reference values are stored in advance in the reference signal generating means, and the /D
Compare the digital output value of the converter with the previously output reference value, and when the digital value is greater than or equal to the previous reference value, output the stored reference value corresponding to the digital value as a new 1c reference value,
On the other hand, when the digital value is smaller than the previous reference value, the memory output of the previous reference value is held, and the reference value is sequentially decreased in steps every time a certain period of time elapses, and the reference signal obtained in this way is Comparison of digital video signals
Since a multivalued signal including a valued signal is obtained, the reference signal generation circuit is entirely composed of digital elements, so there is no need for adjustment unlike in the conventional analog system, and my husband had to ask me about the white parts. It is possible to accurately generate a reference signal that follows directly and follows the point portion with an appropriate delay. The follow-up characteristic of the reference signal for the black portion at t# can be freely determined as necessary. Even when the video frequency is changed, there is no need to re-adjust the charge/discharge time constants as in conventional analog systems. , even if you change the video frequency, M iJM
A reference signal for binarizing a video signal can be created without the need for supervision.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing one embodiment of the present invention, Fig. 2 is a signal waveform 1 showing the operation of Fig. 1, and Fig. 3 is a circuit block diagram showing another embodiment of the invention. , Figure 4 is the third
A signal waveform diagram showing the operation of @, Figure 5 is a schematic explanatory diagram of a conventional optical character reading device, Figure 6 is an explanatory diagram of an analog video signal obtained from an image scanner, and Figure 7 is an analog standard diagram. FIG. 8 is a circuit diagram of a conventional peak hold circuit that generates a signal. FIG. 8 is a signal waveform diagram of a reference signal and a video signal by the conventional circuit. 1... Human/D converter 2... Reference signal generation section 3,
4.7.10...ROf'v1 5, 11...Latch 6...AND gate 8...Counter 9...
・Inverter 12.14... Connoctor 15... Or gate

Claims (1)

[Scope of Claims] An A/D converter that converts an analog video signal into a digital signal, a plurality of reference values stored in advance, and a digital output value of the A/D converter and a previously output reference value. When the digital output value is greater than or equal to the reference value, the memory reference value corresponding to the digital value is output as a new reference value, and when the digital value is smaller than the previous reference value, the memory output of the previous reference value is retained. and a reference value generating means that sequentially decreases the reference value every time a certain output time elapses; and comparing the digital output of the A/D converter and the reference output of the reference value generating means, and 1. A video signal processing device comprising: comparison means for outputting a multivalued signal.