JPH0441389B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a video signal processing device that converts an analog video signal obtained by scanning with an optical character reader or the like into a binary signal corresponding to a white level and a black level. (Prior Art) Conventionally, in optical character reading devices and the like, as shown in FIG. Image Scanner 24
The image scanner 24 performs line scanning to create an analog video signal that is photoelectrically converted, and the signal processing circuit 25 performs signal processing to binarize the digital video signal corresponding to the white level and black level. Characters read optically are recognized based on binary data. By the way, the analog video signal obtained from the image scanner 24 is as shown in FIG.
Due to the influence of the light source and lens, a signal with a bright center is obtained, and this phenomenon is usually known as shading. Even if this shading is corrected, the signal shown in Figure 6b
As shown in the figure, variations in brightness remain in the analog video signal, and accurate signal processing cannot be performed by binarizing it by comparing it with a fixed reference level. Therefore, in order to create a reference signal that follows changes in the analog video signal, a peak hold circuit shown in FIG. 7 is used for signal processing. The peak hold circuit shown in FIG. 7 includes a signal holding capacitor C ₁ between buffer amplifiers 26 and 27.
The capacitor C ₁ is charged quickly by the diode D ₁ , while the capacitor C ₁ is discharged slowly by passing through the resistor R ₁ . In other words, the peak hold circuit has the characteristic of following the white part of the background by charging with a fast time constant, and following the black part corresponding to the characters by discharging with a slow time constant, as shown by the broken line in Figure 8. Obtain the peak hold output. The output of this peak hold circuit is connected to resistor _R2
R3 divides the voltage to a specified signal level, sets a reference level Vr that follows changes in the analog video signal in the comparator 28, and compares it with the analog video signal using the comparator 28, for example, the white part is L level, and the black part is L level. A binary output V ₀ of H level is obtained. (Problem to be Solved by the Invention) However, in such conventional analog signal processing, the charging/discharging characteristics of the peak hold circuit that creates the reference value are different from those of diodes, capacitors,
Since the voltage was determined by a resistor, voltage adjustment had to be performed using a number of adjustment means such as variums to compensate for variations in each element, and analog-specific compensation such as temperature changes had to be made. Ta. Furthermore, the charging time constant of the peak hold circuit must be made faster in order to track the white area due to paper surface noise, variations in image scanner sensitivity, variations in the distribution of light source light intensity, etc.
There is a limit to how high the speed can be increased, and when it becomes necessary to change the video frequency, there is a problem in that the time constant of the peak hold circuit must be readjusted. (Means for Solving the Problems) The present invention has been made in view of these conventional problems, and provides a standard for proper binarization that follows analog video signals without requiring any circuit adjustment. In order to generate a signal, an analog video signal is converted into a digital signal by an A/D converter, a plurality of reference values are stored in advance in the reference signal generating means, and the digital output value of the A/D converter is stored in advance. and the previously output reference value, and if the digital value is greater than or equal to the previous reference value, the stored reference value corresponding to the digital value is output as a new reference value, while on the other hand, the digital value is smaller than the previous reference value. Sometimes, the memory output of the previous reference value is held, and the reference value is sequentially decreased stepwise every time a certain period of time elapses, and the reference value from such a reference value generation means and the digital output of the A/D converter are stored. The digital video signal is converted into a multivalued signal, which is higher than a binary signal, by comparing the two values with a comparison means. (Embodiment) FIG. 1 is a circuit block diagram showing an embodiment of the present invention. First, to explain the configuration, 1 is an A/D converter that converts an analog video signal obtained by an image scanner into a digital video Vi, and the digital video signal Vi output from the A/D converter 1 is a reference The signal generator 2 and the reference signal are supplied to a ROM 3 which serves as a comparison means for outputting a multi-level signal V ₀ by comparing the reference signal and the digital video signal. The reference signal generator 2 has a function of generating a reference signal Vr that changes in accordance with the digital video signal Vi, and is composed of ROMs 4, 7, 10, a latch 5, an AND gate 6, a counter 8, and an inverter 9. . Each circuit element in this reference signal generating section 2 will be explained as follows. The ROM 4 is given the digital video signal Vi and the output signal V _r1 of the ROM 7, which will be explained later. Based on the magnitude relationship between the digital video signal Vi and the output signal V _r1 , the reference signal V r is determined based on the following relational expression. of
Output to ROM3. When Vi≧V _r1 , Vr=Vi When Vi<V _r1 , Vr=V _r1 (1) That is, when the digital video signal _Vi1 is greater than or equal to the output signal V _r1 of the ROM7, the digital video signal Vi is used as the reference signal Vr. output, while digital video signal
When Vi is smaller than the output signal V _r1 of the ROM 7, the reference signal Vr is output as the output signal V _r1 . Digital video signal in ROM4 like this
Reference signal Vr based on comparison of Vi and output signal V _r1
The output of is the digital video signal Vi and the output signal V _r1
This can be realized by storing in the ROM 4 a table memory with table address data. That is, a memory table is created with each digital bit of the signals Vi and V _r1 as addresses, and the data area of the table position determined by the specific values of Vi and V _r1 is populated with Vi or
By writing the value of V _r1 in advance and specifying the data position in the table memory using Vi and V _r1 as address data, Vi or V _r1 based on the magnitude relationship between the two can be read out as the reference signal Vr. In other words, the ROM 4 stores in advance a plurality of reference signals V _r used for comparison with the digital video signal Vi. Also, ROM4 is
It is equipped with an output terminal for the MSB bit, and this MSB bit is used to output the digital video signal Vi and the output signal of ROM7.
Based on the magnitude relationship with _Vr1 , the MSB bit output is generated as follows. When Vi≧V _r1 , MSB=1 When Vi<V _r1 , MSB=0 (2) Next, latch 5 converts the previous reference signal Vr given to ROM3 based on the MSB bit output of ROM4 to the next one. It has a latch function to generate a reference signal. That is, the latch control of the latch 5 is performed by the output of the AND gate 6;
The same clock pulse CK as the clock pulse for A/D conversion used in the MSB bit output of ROM 4 and A/D converter 1 is given, and the H level output when the MSB bit becomes "1", that is, Vi≧ V _r1
At the same time, the reference signal Vr for the ROM 3 is latched and outputted as a latched signal V _r2 . On the other hand, the MSB bit becomes "0". When Vi<V _r1 , the output of AND gate 6 is at L level, so the reference signal
Vr is not latched, and the previously latched reference signal is output as is as the latched signal V _r2 . Note that the latch 5 is cleared each time a horizontal synchronization signal is obtained. Next, ROM7 outputs counter 8 to latch signal Vr.
A signal V _r1 determined by multiplying by a coefficient β determined by the ROM 10 is generated as follows: V _r1 =β·V _r2 (3). Here, the value of the coefficient β according to the above equation (3) is determined by the ROM 10 obtained by the counter 8.
It is determined by the output of First, the counter 8 is connected to the inverter 9.
The MSB bit output of ROM4 is given,
When MSB=0, that is, VI<V _r1 , the H of inverter 9
At the level output, the counter 8 provides a count output to the ROM 10 which performs a counting operation of the clock pulse CK. The ROM 10 generates memory outputs such as 00, 01, 10, 11, etc. every time the output of the counter 8 reaches a predetermined value, and according to the memory outputs of the ROM 10.
The value of the coefficient β of the equation (3) in the ROM 7 is determined. For example, the value of the coefficient β of the ROM7 with respect to the output of the ROM10 is predetermined as shown in Table 1 below.

【table】 …

Claims (1)

[Scope of Claims] 1. An A/D converter that converts an analog video signal into a digital signal; and a plurality of reference values that are stored in advance, and a digital output value of the A/D converter and a previously output reference value. When the digital output value is greater than or equal to the reference value, the memory reference value corresponding to the digital value is output as a new reference value, and when the digital value is smaller than the previous reference value, the memory output of the previous reference value is retained. and a reference value generating means that sequentially decreases the reference value every time a certain output time elapses, and compares the digital output of the A/D converter with the reference output of the reference value generating means and determines the video level. 1. A video signal processing device, comprising: comparison means for outputting a corresponding multi-level signal.