JPS6149446A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS6149446A
JPS6149446A JP59171856A JP17185684A JPS6149446A JP S6149446 A JPS6149446 A JP S6149446A JP 59171856 A JP59171856 A JP 59171856A JP 17185684 A JP17185684 A JP 17185684A JP S6149446 A JPS6149446 A JP S6149446A
Authority
JP
Japan
Prior art keywords
semiconductor element
lead frame
heat
heat dissipation
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59171856A
Other languages
English (en)
Inventor
Koji Nose
幸之 野世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP59171856A priority Critical patent/JPS6149446A/ja
Publication of JPS6149446A publication Critical patent/JPS6149446A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、樹脂封止型半導体装置に関し、詳しくは、パ
ッケージの中に半導体素子と一緒に搭載される放熱部品
の配置、構造、係るものである。
従来例の構成とその問題点 従来の樹脂封止型半導体装置に見られるように、半導体
素子に流れる電流により生じるジーール熱の放散は、パ
ッケージの表面か裏面にフィン付き放熱部品や平面放熱
板を取り付けるか、放熱部品を封止樹脂中の、半導体素
子を搭載したリードフレームの裏側に埋め込むことによ
って行なわれる。
しかし発熱の大部分は、半導体素子中の電流の流れる部
分、すなわち半導体素子の配線パターン形成面側である
。そのために放熱を妨げる因子の熱抵抗が、シリコン基
体の厚さ方向の熱抵抗（Ｒｔｈｓｉ）と、リードフレー
ムの厚さ方向の熱抵抗（ＲｔｈＦ）と、シリコン基体と
リードフレームとを接続している接着物の熱抵抗（Ｒｔ
ｈＡ）と、リードフレームと放熱部品とを接続している
接着物の熱抵抗（ＲｔｈＢ）との総和（ＲｔｈＣ）　Ｉ
Ｒｔｈｓｉ＋ＲｔｈＦ＋ＲｔｈＡ＋ＲｔｈＢで作用する
。従って熱抵抗は、従来のパッケージ表面に放熱部品を
取り付けた場合、半導体素子表面からパッケージ表面ま
での熱抵抗（ＲｔｈＲ）が非常に大きいため、放熱効果
が低い。さらに封止樹脂中に埋め込んだ場合は、Ｒｔｈ
Ｃとなシ、ＲｔｈＲより放熱効果は良いが、更に熱抵抗
を下げたい時、問題となってくる。
発明の目的 本発明は熱抵抗の低い樹脂封止型半導体装置の一製造方
法を提供するものである。
発明の構成 本発明は要約するに、半導体素子の配線パターン形成面
側に放熱部品を接着層を介して前記配線パターンと絶縁
的に取りつけたもので、これによシ、放熱効果の高い樹
脂封止型パッケージを達成することができる。
実施例の説明 第１図に本発明による樹脂封止型半導体装置の断面、第
２図に、矢印順に進行する工程順断面図を示した。まず
リードフレームのダイパッド１に半導体素子２を、たと
えば１．Ａｕ−３ｉ共晶や半導電性エポキシペースト等
のダイ接着剤３を介在させて搭載し、これにＡｕやＡＩ
の細線４でリードフレームのインナーリード５と半導体
素子２上のポンディングパッド６とを接続する。
つぎに、ＣｕやＣｕ合金、　ＡＩやＡｇ合金などで形成
され、傾斜角度約４５°の逆台形の放熱部品７を熱伝導
率の高いフィラーを混ぜた液状エポキシ樹脂８に、底面
だけ付着させ、その放熱部品７を半導体素子２の表面に
直接貼シ付け、１３０〜１８０℃の窒素雰囲気中で硬化
させる。この状態でエポキシ樹脂９でトランスファー成
形する。その際、リードフレーム材料と、エポキシ樹脂
材料に熱伝導率の良好なものを使用することで、熱抵抗
の著しく改善されたパッケージ構造が達成できる。なお
、第２図中、放熱部品７の傾斜角度θは、０≦θ≦１５
０　の範囲で選択可能である。
発明の効果 本発明によれば、樹脂封止型パッケージで問題となって
いた、パッケージ熱抵抗の大幅な改善がなされ、半導体
素子の消費電力限界の制限が、−挙に解決できる。
【図面の簡単な説明】
第１図は本発明の樹脂封止型半導体装置の断面図、第２
図は本発明実施例装置の工程順断面図である。 １・・・・・・リードフレームダイパッド、２・・・・
・・半導体素子、３・・・・・・グイ接着剤、４・・・
・・・細線、５・・・・・・リードフレームインナーリ
ード、６・・・・・・ポンディングパッド、７・・・・
・・放熱部品、８・・・・・・液状エポキシ樹脂、９・
・・・・・封止用エポキシ樹脂。

Claims (1)

    【特許請求の範囲】
  1. 　半導体素子の配線パターン形成面側に放熱部品を接着
    層を介して前記配線パターンと絶縁的に取り付けたこと
    を特徴とする樹脂封止型半導体装置。
JP59171856A 1984-08-17 1984-08-17 樹脂封止型半導体装置 Pending JPS6149446A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59171856A JPS6149446A (ja) 1984-08-17 1984-08-17 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59171856A JPS6149446A (ja) 1984-08-17 1984-08-17 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS6149446A true JPS6149446A (ja) 1986-03-11

Family

ID=15931047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59171856A Pending JPS6149446A (ja) 1984-08-17 1984-08-17 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS6149446A (ja)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02307251A (ja) * 1989-05-22 1990-12-20 Nec Corp 樹脂封止型半導体装置
JPH07321252A (ja) * 1994-05-19 1995-12-08 Nec Corp 樹脂封止型半導体装置
US5530295A (en) * 1993-12-29 1996-06-25 Intel Corporation Drop-in heat sink
US5625226A (en) * 1994-09-19 1997-04-29 International Rectifier Corporation Surface mount package with improved heat transfer
GB2344934A (en) * 1995-10-24 2000-06-21 Altera Corp Integrated circuit package
US6444498B1 (en) * 2001-08-08 2002-09-03 Siliconware Precision Industries Co., Ltd Method of making semiconductor package with heat spreader
WO2002052645A3 (en) * 2000-12-22 2003-05-30 Broadcom Corp Enhanced die-up ball grid array packages and method for making the same
US6876553B2 (en) 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US7078806B2 (en) 2002-02-01 2006-07-18 Broadcom Corporation IC die support structures for ball grid array package fabrication
US7202559B2 (en) 2000-12-22 2007-04-10 Broadcom Corporation Method of assembling a ball grid array package with patterned stiffener layer
US7241645B2 (en) 2002-02-01 2007-07-10 Broadcom Corporation Method for assembling a ball grid array package with multiple interposers
US7402906B2 (en) 2001-02-15 2008-07-22 Broadcom Corporation Enhanced die-down ball grid array and method for making the same
US7411281B2 (en) 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7432586B2 (en) 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7482686B2 (en) 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7629681B2 (en) 2000-12-01 2009-12-08 Broadcom Corporation Ball grid array package with patterned stiffener surface and method of assembling the same
JP2017034131A (ja) * 2015-08-03 2017-02-09 エスアイアイ・セミコンダクタ株式会社 半導体装置及びそれを有する実装基板

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02307251A (ja) * 1989-05-22 1990-12-20 Nec Corp 樹脂封止型半導体装置
US5530295A (en) * 1993-12-29 1996-06-25 Intel Corporation Drop-in heat sink
JPH07321252A (ja) * 1994-05-19 1995-12-08 Nec Corp 樹脂封止型半導体装置
US5625226A (en) * 1994-09-19 1997-04-29 International Rectifier Corporation Surface mount package with improved heat transfer
GB2344934A (en) * 1995-10-24 2000-06-21 Altera Corp Integrated circuit package
US7629681B2 (en) 2000-12-01 2009-12-08 Broadcom Corporation Ball grid array package with patterned stiffener surface and method of assembling the same
US7202559B2 (en) 2000-12-22 2007-04-10 Broadcom Corporation Method of assembling a ball grid array package with patterned stiffener layer
WO2002052645A3 (en) * 2000-12-22 2003-05-30 Broadcom Corp Enhanced die-up ball grid array packages and method for making the same
US7402906B2 (en) 2001-02-15 2008-07-22 Broadcom Corporation Enhanced die-down ball grid array and method for making the same
US6444498B1 (en) * 2001-08-08 2002-09-03 Siliconware Precision Industries Co., Ltd Method of making semiconductor package with heat spreader
USRE39957E1 (en) * 2001-08-08 2007-12-25 Siliconware Precision Industries Co., Ltd. Method of making semiconductor package with heat spreader
US7405145B2 (en) 2001-12-18 2008-07-29 Broadcom Corporation Ball grid array package substrates with a modified central opening and method for making the same
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US7241645B2 (en) 2002-02-01 2007-07-10 Broadcom Corporation Method for assembling a ball grid array package with multiple interposers
US7078806B2 (en) 2002-02-01 2006-07-18 Broadcom Corporation IC die support structures for ball grid array package fabrication
US6887741B2 (en) 2002-03-21 2005-05-03 Broadcom Corporation Method for making an enhanced die-up ball grid array package with two substrates
US7312108B2 (en) 2002-03-21 2007-12-25 Broadcom Corporation Method for assembling a ball grid array package with two substrates
US6876553B2 (en) 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US7411281B2 (en) 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7432586B2 (en) 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7482686B2 (en) 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7595227B2 (en) 2004-06-21 2009-09-29 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
JP2017034131A (ja) * 2015-08-03 2017-02-09 エスアイアイ・セミコンダクタ株式会社 半導体装置及びそれを有する実装基板

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