JPS6150433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a text signal receiving circuit that allows a microcomputer installed in a television receiver to function as a text broadcast receiving device for program reservations and video game execution.

A microcomputer usually has a CPU, ROM,
It consists of a RAM and an interface, and based on commands input from the interface, the program in the ROM is input to the CPU, the program is executed, and the execution output is led to the outside via the interface. However, the execution speed of the CPU is slow and it is not possible to directly derive the signals displayed on the television screen, so in order to run video games etc.
Separate reading means is required. The configuration of the reading means will be explained below in accordance with the circuit operation for causing the microcomputer to execute a television game. FIG. 1 shows a circuit connection for executing a video game. First, when the input device 5 designates one of multiple video games, a game designation signal is sent via the interface 4.
Input to CPU1. The CPU 1 reads from the ROM 2 the game program stored at the address corresponding to the game designation signal. In order to execute the read program, the CPU 1 reads display data corresponding to an image to be displayed first (for example, a court and a racket) from the ROM 2 and stores it in the RAM 3.
Contains display data for writing to
Specify the address of ROM2 and read it once into the accumulator, and specify the corresponding address of RAM3 to write the display data. Furthermore, ROM
and RAM share an address path, and the addresses of both are determined without duplication. Next, the CPU 1 writes a moving image (for example, a ball) into the RAM, executes a program to change the writing position according to a predetermined rule, and also controls the potential AD of variable volumes (usually a pair) provided in the input device. A program is executed to read the conversion value and change the writing address of the operation image (for example, a racket) to the RAM 3. Therefore, the moving image moves two-dimensionally according to a predetermined rule, that is, when the light hits the fixed image and the manipulated image, it bounces off like a reflection. Move one-dimensionally on the screen by operating .

During execution of the above-mentioned program, whenever a timing for displaying an image on the television screen is reached, the operation of the CPU 1 is temporarily stopped and the information stored in the RAM 3 is read out for display. The RAM is usually composed of 8 storage elements corresponding to the number of data paths, and 1 bit of data is written to a common address for each element, and when reading, 8 storage elements are written at a time.
It is derived using bit output as a unit. Therefore, if the display frequency in a video game is 3.58MHz, it can be displayed by specifying the read address in synchronization with the frequency 447.5KHz, which is 1/8 of 3.58MHz, and converting the parallel 8-bit information into serial data. become.

As shown in the figure, a clock pulse generation circuit 6 derives display pulses from the output of a synchronization signal generation circuit 8 which generates a synchronization signal for television signals.
The address counter 9 that counts the output is connected to the RAM.
Address 3 is specified and 8 bits of information is input to the diplexer 7 which enables a shift register, the read information is input to the mixing circuit 10 in synchronization with the display pulse, and the mixed output with the synchronizing signal is used for television reception. It is input into the machine and displayed. Said CPU1
Pause is effected by inputting a command signal generated by the address counter 9 to the CPU 1 in conjunction with the address designation operation of the address counter 9.

The present invention aims to propose a specific circuit connection that allows a microcomputer configured as described above to function as a character signal receiving circuit.

An embodiment of the present invention configured to receive character signals from a telescan system will be described below with reference to the circuit block diagram shown in FIG. The circuit block diagram in this embodiment has some of the same figure numbers as the circuit block diagram in Figure 1 in order to avoid duplication with the explanation regarding the execution of the television game. Only the circuit operation for performing this will be explained. First, when receiving a character signal, when the output of the program selection input circuit 15 is input to the CPU 1 via the interface 4, the CPU 1
contains programs for receiving teletext broadcasting.
The program is read into the CPU 1 by specifying the ROM address and executed. In order to execute the teletext reception program, first, a switching signal is input from the interface 4 to the signal switching gate 12, and the synchronization signal input to the mixing circuit 10 is switched to a video signal. The synchronization signals input to the CPU 1 are counted, and an output corresponding to the 20th horizontal scanning section is derived from the interface 4, and the 20H sampling gate 14 is opened. When the 20H extraction gate 14 is opened, 80 bits of the character signal for five channels are stored in one RAM via one data path, which is superimposed on the vertical retrace section. To specify a write address for storing a character signal, first set it so that the write clock is generated approximately at the center of the initial flag preceding the character signal.
After the clock generating circuit 6 is phase-controlled by a bit synchronization circuit 11, a write clock is input to the address counter 9'. The address counter 9' detects the input of the write clock, issues a pause output, temporarily cuts off the address output of the CPU 1, and
The 80 bits output from the 20H extraction gate 14 are stored in one RAM element in the write state by the CPU 1 at the write address designated by the address counter 9'. After writing is completed, the address counter 9'
When the pause output is deactivated, the CPU 1 executes the subsequent program for teletext reception. Therefore, first, 16-bit character signals of the channel specified by the program selection input circuit 15 are input to the CPU 1. Subsequently, the character signal is stored in the RAM 3 at an address corresponding to the display position. During reading, a 7.16 MHz read clock whose phase is controlled by the synchronization separation output and is synchronized with the video signal is derived from the clock generation circuit 6 and inputted to the address counter 9' and the diplexer 7. The address counter 9' detects the read clock and issues a pause output to stop the address output of the CPU 1, and inputs the lower 3 bits of the count output to the diplexer and the remaining upper output to the RAM 3 as a read address. do. 7.16/8MHz from the data path by specifying the read address
The 8-bit character signals derived at a speed of 1 are sequentially input to the diplexer 7, and are derived in synchronization with the read clock in the order designated by the 3-bit output of the address counter 9'. The character signal derived from the diplexer 7 is superimposed with a video signal in the mixing circuit 10, and an image with the characters superimposed thereon is projected on the cathode ray tube. By performing the above operation for each field and sequentially changing the display start address, the character pattern can be moved from left to right without changing the writing position in the RAM for each field.

As described above, the character signal receiving circuit of the present invention temporarily stores the received character signal in the random access memory in the microcomputer, and then converts the stored character signal to the character according to the execution of the program of the microcomputer. Since the signal is re-stored at an address in the memory suitable for reading for display, there is no need for a buffer memory for temporary storage of the received character signal, and the character signal that separates the character signal from the video signal Since the signal separation circuit can also be operated by the microcomputer, the number of component circuits required other than the microcomputer can be reduced, and the connection between these circuits and the microcomputer can be simplified, and can therefore be realized at low cost. This is particularly suitable when the microcomputer is used both for receiving text signals and for playing video games.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing circuit connections for causing a microcomputer to execute a video game, and FIG. 2 is a circuit block diagram showing an embodiment of the present invention. Explanation of the main drawing numbers: 1...Center process unit (CPU), 3...Random access memory (RAM), 14...20H extraction gate.

Claims (1)

[Claims] 1. In a character signal receiving circuit that separates a character signal superimposed on a composite video signal, stores it in a random access memory in a microcomputer, reads it out in synchronization with the video signal, and displays the character signal superimposed on the video signal. , the character signal separation circuit is operated by counting the synchronization signal in the composite video signal in the center process unit of the microcomputer, and the character signal derived from this separation circuit is directly stored in the memory. After that, as the process unit executes the program, the character signal is read out from the memory into the process unit, and the character signal is stored again at an address in the memory suitable for reading for display. A character signal receiving circuit characterized in that: