JPS6154265B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a compound semiconductor device, particularly a Schottky junction field effect transistor device using a compound semiconductor GaAs as a base material.

It is known that field-effect transistors based on the compound semiconductor GaAs can exhibit much better performance in the application range of ultra-high frequency and ultra-high speed signal processing than those based on ordinary Si. has been
As a recent trend in the development of information equipment, there are great expectations for the development of high-density integration devices.

On the other hand, the ultra-high frequency of field effect transistor devices,
The basic requirements for ultra-high speed are firstly to reduce the thickness of the active layer and precisely control it, and secondly to reduce the gate length and source-drain distance as much as possible. shortening and precise control of relative position,
Third is the incorporation of an n ⁺ layer to reduce ohmic connection resistance in the source and drain electrode regions.
Such a configuration, especially in the case of high-density integrated equipment, cannot be achieved only by improving manufacturing technology; it is essential to make a leap forward based on new ideas from the equipment structural design and manufacturing process design. .

Now, FIG. 1 is a diagram for explaining a conventional manufacturing method of a Schottky junction field effect transistor device using GaAs as a base material. As shown in this figure, conventionally, an n-type GaAs layer 2 is formed on the entire surface of a semi-insulating GaAs substrate crystal 1 by an epitaxial method.
Using an epitaxial substrate on which an n ⁺ type GaAs layer 3 is formed, a device area is set by mesa etching. Further, after providing the source and drain electrodes 4 and 5, an active layer region 6 is set by etching the n ⁺ type GaAs in the gate electrode region and expanding the etching in the lateral direction using the electrode metal as a mask, and then A shot-to-junction gate electrode 7 is formed by vapor deposition using a metal mask.

Such a conventional manufacturing method is the most excellent method for realizing a high-performance single element for ultra-high frequency bands. However, this manufacturing method has substantial drawbacks with respect to expansion into high-density integrated devices for the following reasons. Firstly, because the device area is set by mesa etching using a full epitaxial substrate, and because a relatively thick epitaxial layer must be used for reasons explained later, it is difficult to achieve high density integration. The required planarization is extremely difficult. The second drawback is that in the GaAs etch for setting the active layer region 6,
It is necessary to control both the etching amount in the depth direction, which determines the active layer thickness, and the etching amount in the lateral direction, which determines the electrode spacing, in order to prevent short-circuit accidents between electrodes and reduce interelectrode capacitance. For this purpose, a relatively thick n-type or n ⁺ -type layer must be used and a thin active layer must be realized by deep etching. This makes it completely difficult to ensure manufacturing yield and mass productivity due to variations among elements in an integrated device consisting of a large number of elements, even under sophisticated manufacturing control.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a compound semiconductor device that fundamentally solves the fundamental drawbacks of conventional manufacturing methods.

That is, the present invention applies a selective epitaxial layer containing a different compound semiconductor to a shot junction field effect transistor device using GaAs as a base material, and performs aperture etching of an insulating film in each electrode region by one type of resist mask process. The method is characterized in that the thickness of the active layer and the relative positional relationship of the electrode system are automatically set with high precision based on the resulting insulating film pattern. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a basic embodiment of the manufacturing method of the present invention. To explain one embodiment with reference to this diagram, first, in the steps up to FIG. 2a, SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ etc. insulating film 12
A resist mask 13 is provided and the insulating film 12 in the device area is etched.

Next, in order to selectively bury the epitaxial growth, etching grooves are formed in the substrate crystal 11 in the openings of the insulating film 12 in the device area, and then in the process shown in FIG. n-type GaAs layer 14 for the groove for the area fenestration, n ⁺ type GaAlAs
Three selective epitaxial layers, layer 15 and n ⁺ type GaAs layer 16, are formed. Here, the n-type GaAs layer 14 constitutes an active layer, and is typically an n-type GaAs layer 14.
The density is set at 1 to 2×10 ¹⁷ /cm ³ and the thickness is set to 0.1 to 0.3 μm. Further, the n ⁺ type GaAlAs layer 15 and the GaAs layer 16 are both used to obtain low ohmic electrode connection in the source and drain electrode regions, and typically each has an impurity concentration of 10 ¹⁸ /cm ³ or more, Thickness 0.2~0.3μ
It is set to about m. In addition, n ⁺ type in the middle layer
The reason for providing the GaAlAs layer 15 is as described later.
This is to perform selective etching between the GAs layers 14 and 16 to exhibit one important feature of the present invention.

In addition, as a method of etching the substrate crystal 11 for selectively burying the epitaxial growth described above, commonly used solution etching method or gas phase reaction etching method can be easily applied, and the etching depth can be easily applied. The thickness is roughly approximated to the sum of the growth thicknesses of the three layers mentioned above. Furthermore, as an epitaxial growth method, it goes without saying that the usual liquid phase method (LPE) or vapor phase method (VPE) can be applied, but the MO-CVD method or molecular beam method, which has recently been rapidly developed, can also be used. Particularly effective is the epitaxial method (MBE). Incidentally, the MO-CVD method involves growing single crystals of compound semiconductors through a gas phase reaction between organic metals such as trimethylgallium and trimethylaluminum and aldine (AsH ₃ ). Furthermore, the MBE method grows single crystals by irradiating each elemental atom of a compound semiconductor onto a substrate in the form of molecular beams.

After that, in the step shown in FIG. 2c, the insulating film 12 used in the previous step is removed by etching, the entire surface is covered with the insulating film 17, and a resist mask 18 is used to simultaneously set the source, drain, and gate electrode regions.
Then, etching is performed to open the insulating film 17 in each electrode area. The pattern of the insulating film 17 formed in this step is maintained until the subsequent step shown in FIG.

Next, in the step shown in FIG. 2d, a resist mask 19 is provided to cover the insulating film 17 in the source and drain electrode regions except for the fenestrations in order to form a good ohmic contact with the n ⁺ type GaAs layer 16. Au―
Vapor deposition and lift-off of Ge alloy or Au-Ge-Ni alloy are performed to form source and drain electrodes 20.
and 21.

Next, in the step shown in FIG. 2e, the resist mask 2
2 is provided to cover the insulating film 17 in the gate electrode area except for the fenestration, and the n ⁺ type GaAs layer 16 and
By etching the n ⁺ type GaAlAs layer 15, precision molding of the active layer, which is one of the features of the present invention, is achieved. In the first step of the etch treatment in this process, an etchant having a selective etch action that etches only the n ⁺ type GaAs layer 16 and does not etch the GaAlAs layer 15 at all is used. Such an etching solution is a mixture of aqueous ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ), with a mixing ratio of approximately 1:
A composition having a composition of 10 or more is suitable. The second stage of the etch process is performed using a selective etchant that etches only the n ⁺ type GaAlAs layer 15 and does not react with the GaAs layer 14. Such etchants include hydrochloric acid (HCl) and phosphoric acid. A 1:1 mixture with (H ₃ PO ₄ ) is preferred.

In addition, in the two-step selection process mentioned above,
The etching in the depth direction stops when it reaches the interface between different semiconductors, and from then on, only the etching in the lateral direction proceeds. Therefore, the thickness of the active layer is always the same as the initial epiaxial layer thickness. The length of the active layer between the source and drain electrode regions can be set arbitrarily while maintaining the length.

Next, in the step shown in FIG. 2f, a Schottky junction forming metal such as Al is deposited using the pattern of the insulating film 17 as a mask, and the gate electrode 23 is formed in an automatically aligned state, and the source and This metal coating 2 is also applied to the drain electrode part at the same time.
4 and 25 are formed. Upon completion of the above process, the insulating film 17 pattern, which has played the role of automatic alignment of the relative positional relationship of the electrode system, is removed as part of the lift-off process.

After that, in the step shown in FIG. 2g, an insulating film 26 is provided as a protective film for surface stabilization or as an interlayer insulating film for electrode wiring of an integrated device. A type field effect transistor device is completed.

As explained in detail in the above embodiment, in the manufacturing method of the present invention, first, the device area is n-type.
It is composed of three selective epitaxial layers: GaAs, n ⁺ type GaAlAs, and n ⁺ type GaAs, and the active layer shape is set by selective etching between different semiconductor layers (selective etching with a GaAlAs layer in the middle). . Therefore, the active layer thickness is now fully guaranteed to be a constant thickness equal to the initial n-type GaAs epitaxial layer thickness, which improves the yield due to improved property uniformity and reduced variation. contribute directly to Furthermore, since the amount of etch in the lateral direction can be set regardless of the amount of etch in the depth direction, a sufficiently thin n ⁺ type layer is sufficient to form a predetermined active layer length; Combined with the effects of the selective epitaxial method and the embedded selective epitaxial method, this method is of great help in realizing the planarized structure essential for high-density integrated devices.

Second, in this invention, an insulating film pattern that simultaneously sets the source, drain, and gate electrode regions is formed using one type of resist mask during the manufacturing process, and this insulating film pattern is used as the electrode system in each subsequent process. By using it as a reference for the formation of the structure, it is possible to automatically align the relative positions of the electrode systems. This provides a highly precise manufacturing method for the microstructuring of electrode systems that will lead to higher performance and higher density integration of devices, and will improve device uniformity, yield, and productivity. It directly contributes to the improvement of In addition, the automatic alignment vapor deposition method of shot-type junction metal using an insulating film pattern as a mask, along with the rational formation method of the active layer shape described above, has the advantage of creating gates with less stray capacitance and less structural irregularities. This material is highly useful for improving the performance of high-density integrated devices, making it easier to coat surface stabilizing insulating films or electrode wiring interlayer insulating films, and improving reliability.

Further, according to the method of the present invention, since crystal growth is performed only in a limited device area, mesa etching for isolation between elements is not required. On the other hand, in the case of full-surface epitaxial growth, a mesa etch is essential, and the difference in etch rate in the multilayer epitaxial growth layer of different compound semiconductors conversely causes harmful unevenness in the shape of the side surface of the mesa etch. There is a drawback that it can cause accidents such as disconnection of the wiring pattern. According to the method of the present invention, this drawback can be completely eliminated.

Furthermore, in the method of the present invention, buried type selective epitaxial growth is performed, and in this buried type selective epitaxial growth technique, growth conditions such as the crystal axis of the substrate crystal and the substrate temperature are selected. As a result of the interrelationship between the growth from the side and bottom sides of the trench, the continuity of the crystal around the buried part is very good, making it extremely suitable for the planar configuration of the device. .

Furthermore, according to the method of this invention, GaAs and
By using selective etching technology with GaAlAs, any active layer length can be obtained without changing the surface shape of the gate region, and the active layer length can be precisely controlled. It is. That is,
According to the method ^of this invention, n ⁺
GaAs layers are stacked. The shape of this n ⁺ type GaAs layer is determined by the first selective etching of the layer. Therefore, then n ⁺ form
Even if a second selective etch of the GaAlAs layer is performed to obtain an active layer of arbitrary length by lateral etching, the surface shape of the gate region remains unchanged in the n ⁺ shape.
The GaAs layer ensures the desired shape. In addition, both the n ⁺ type GaAlAs layer and the n ⁺ type GaAs layer are compound semiconductors and have good adhesion, so the etching solution will not seep in from the mutual interface and cause ^abnormal etching. The amount of directional etching, in other words, the length of the active layer can be precisely controlled.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining a conventional manufacturing method of a Schottky junction field effect transistor device using GaAs as a base material, and FIGS. 2 a to 2 g are an embodiment of the method of manufacturing a compound semiconductor device according to the present invention. FIG. 11... Semi-insulating GaAs substrate crystal, 12... Insulating film, 13... Resist mask, 14... N-type
GaAs layer, 15...n ⁺ type GaAlAs layer, 16...n ⁺
GaAs layer, 17... Insulating film, 18, 19... Resist mask, 20, 21... Source and drain electrodes, 22... Resist mask, 23... Gate electrode, 24, 25... Covering, 26... Insulating film.

Claims (1)

[Claims] 1 A groove is formed in the device area of a semi-insulating substrate or a semi-insulating substrate having a buffer layer, and an n
GaAs active layer, n ⁺ GaAlAs layer and n ⁺ GaAs
The layer is buried by selective epitaxial method,
Provide an insulating coating and use a resist mask to connect the source and
There is a step of simultaneously etching the insulating film in the drain and gate electrode regions, and a resist mask covering the gate electrode region is used to deposit and deposit the ohmic electrode metal.
The process of forming source and drain electrodes using the lift-off method and the opening of the insulating film in the gate electrode area.
A step of selectively etching the n ⁺ type GaAs and n ⁺ type GaAlAs layers in two steps, and a step of performing evaporation and lift-off of a shot junction metal using the insulating film pattern as a mask to form a gate junction electrode. A method for manufacturing a compound semiconductor device characterized by: