JPS6155138B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device that transfers data from a peripheral device to a storage device.

Conventionally, when transferring data from a peripheral device to a storage device, this type of data transfer device consists of a single address counter that holds the storage address of the transferred data and a single length counter that indicates the number of data to be transferred. When there is one data block from a peripheral device, it is stored in a single area of the storage device, and when there are multiple data blocks, the contents of the address counter and length counter are updated each time the data block is switched. It was modified and stored in multiple areas of the storage device. Therefore, it is not possible to store part or all of the same data block in multiple areas of the storage device during data transfer, so the data block from the peripheral device is stored once at a specific address in the storage device, and then the software The drawback was that the software had to be partially or completely moved to another address.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer device that solves the above-mentioned drawbacks by allowing part or all of the same data block to be stored in different areas of a storage device in one transfer from a peripheral device.

In order to achieve the above object, the data transfer device according to the present invention includes a plurality of address counters that hold storage addresses of data to be transferred, a plurality of length counters that hold the number of data to be transferred corresponding to each address counter, and a plurality of length counters that hold the number of data to be transferred corresponding to each address counter. A plurality of key data registers that hold search data indicating the start position of transfer data corresponding to the address counter of the above are compared with the search data of the plurality of key data registers and data from the peripheral device for each data transfer, and a match is made. The comparison control circuit stores subsequent data in a storage device using an address counter and a length counter corresponding to the key data register.

According to the above configuration, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data transfer device according to the present invention.

In FIG. 1, this embodiment holds the storage address of data to be transferred, and stores the outputs of #1 address counter 2, #2 address counter 3, #1 address counter, and #2 address counter 3, which are incremented by 1 for each transfer, as inputs. A selector 1 that selects the address to be sent to the device, a #1 length counter 4 and a #2 length counter 5 that hold the number of data to be transferred corresponding to the address counters #1 and #2 and decrement the number by 1 for each transfer; #1 key data register 6 and #2 key data register 7 that hold search data indicating the start position of transfer data corresponding to address counters 1 and #2, and a data register 8 that stores data from peripheral devices. It is composed of a comparison control circuit 20. The comparison control circuit 20 #1
a 0 detector 9 that detects that the content of the length counter 4 has become 0; a 0 detector 10 that detects that the content of the #2 length counter 5 has become 0;
A comparison circuit 11 that compares data in #1 key data register 6 and data register 8, a comparison circuit 12 that compares data in #2 key data register 7 and data register 8, and detects the start point of data transfer on the #1 side. #1 search F/F 13 that detects the start point of data transfer on the #2 side
14, #1 transfer F/F 15 indicating that data is being transferred on the #1 side, and #2 indicating that data is being transferred on the #2 side.
Transfer F/F 16, AND circuits 17 and 18,
The #1 transfer F/F 15 and #2 transfer F/F 16 control the interface with the selector 1 and the storage device, and the #1, #2 address counter 2,
The timing of adding +1 to 3, the timing of -1 to #1 and #2 length counters 4 and 5, and the timing of #1,
It includes a control circuit 19 that controls the set and reset timing of the #2 search F/Fs 13 and 14 and the #1 and #2 transfer F/Fs 15 and 16.

Further, S1 and S2 are activation signals for starting operations on the #1 side and #2 side, respectively, S3 is an address signal going to the storage device, S4 is a data signal going to the storage device, and S5 is a data signal from the peripheral device.

#1 address counter 2 has address A, #2 address counter 3 has address B, #1 length counter 4 has N pieces, #2 length counter 5 has M pieces, #1 key data register 6 has search data α.
However, after the search data β is set in the #2 key data register 7, the search F/F1 of #1 and #2
3 and 15 are set by activation signals S1 and S2, the operation is as follows.

First, since the search F/Fs 13 and 15 of #1 and #2 are set, the comparison circuits 11 and 1 of #1 and #2 are set.
2 is enabled. When the data from the peripheral device is stored in the data register 8, #1, #2
Comparison circuits 11 and 12 compare the data with key data registers 6 and 7 of #1 and #2. If the data stored in the data register 8 is α, it matches the #1 key data register 6, the #1 search F/F 13 is reset, and the #1 transfer F/F 15 is reset.
is set, and the #1 side becomes ready for data transfer. Based on the output of #1 transfer F/F 15, control circuit 19 selects #1 address counter 2 with selector 1, sends an address signal S3 with #1 address counter 2 as the address to the storage device, and transfers the data to that address. Write the contents of data signal S4.

After that, #1 address counter 2 is incremented by 1, and #1
Decrement length counter 4 by 1. Repeat the above operation every time data enters data register 8,
This continues until the #10 detector 9 detects that the #1 register counter 4 becomes 0 and the #1 transfer F/F 15 is reset.

If the data β from the peripheral device is stored in the data register 8 before #10 detector 9 detects 0, it will match with #2 key data register 7, so
The #2 search F/F 14 is reset, the #2 transfer F/F 16 is set, and the #2 side also becomes ready for data transfer.

Since both #1 and #2 transfer F/Fs 15 and 16 are set, the control circuit 19 first selects #1 address counter 2 with selector 1, and sets #1 address counter 2 to the storage device. The address signal S3 is sent to write the contents of the data signal S4 at that address. Next, selector 1 selects #2 address counter 3, sends an address signal S3 with #2 address counter 3 as the address to the storage device, and writes the contents of data signal S4 at that address in the same way as on the #1 side. It's crowded.

In this way, the contents of the data register 8 are written to the addresses indicated by the #1 address counter 2 and the #2 address counter 3.

After that, set the #1 and #2 address counters to +
1, and the #1 and #2 length counters are each decremented by 1.

On the #2 side, the process is repeated until the #2 length counter 5 becomes 0. When the #2 length counter 5 becomes 0, the #2 transfer F/F 16 is reset and the process ends. By the above operation, from address A to N of the storage device
This means that part or all of the same data block is stored in M areas and M areas from address B.

In this embodiment, the case of two sets #1 and #2 has been described, but it can be implemented in the same way with two or more sets.

As explained above, the device according to the present invention has a plurality of address counters, register counters, and key data registers, and is configured so that the storage address, the number of stored data, and the start time of data transfer can be arbitrarily set. Some or all blocks can be stored in multiple areas on the storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data transfer device according to the present invention. 1... Selector, 2, 3... #1, #2 address counter, 4, 5... #1, #2 length counter, 6, 7... #1, #2 key data register, 8... data register ,9,10...#1,
#20 Detector, 11, 12...#1, #2 Comparison circuit, 13, 14...#1, #2 Search F/F, 1
5, 16...#1, #2 transfer F/F, 17, 18
...AND circuit, 19...control circuit, 20...comparison control circuit, S1, S2...#1, #2 starting signal, S3...address signal, S4, S5...data signal.

Claims (1)

[Claims] 1. A plurality of address counters that hold the storage address of the data to be transferred in the storage device, a plurality of length counters that hold the number of data to be transferred corresponding to each address counter, and a plurality of length counters that hold the number of data to be transferred corresponding to each address counter. A plurality of key data registers that hold search data indicating the start position are compared with the search data and transfer data of the plurality of key data registers for each data transfer, and the address counter and length corresponding to the key data register that match are compared. 1. A data transfer device comprising: a comparison control circuit that uses a counter to store subsequent data at an address of a storage device indicated by each matching address counter.