JPS6351380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array type master slice integrated circuit (LSI) that forms various logic circuits by changing only the wiring process. This relates to improving the delay time of the internal gate that drives the output buffer in circuits configured with (ECL) circuits.

Figure 1 is a gate array type master slice LSI
FIG. 2 is a diagram showing a general configuration of. In the figure, 101~
Reference numeral 104 denotes a master pattern forming area for internal gates, which is arranged for a large number of gates in each row. 1
Reference numerals 11 to 114 designate master pattern forming regions for input buffers or output buffers, each of which is arranged for a large number of gates. By forming circuit elements such as transistors and resistors in advance by using all pre-wiring processes in common in these master pattern forming areas, and changing only the wiring process,
Various logic circuits are constructed by creating various logic gates and at the same time providing wiring between each gate.
Note that the wiring within the gate is provided on the master pattern, and the wiring between the gates is provided on the wiring area other than the master pattern.

FIG. 2 shows an equivalent circuit diagram of the internal gates and output buffers that make up a conventional gate array type master slice LSI using an ECL circuit. In the figure,
A and B correspond to the internal gate and output buffer, respectively. In this figure, the internal gate has a 3-input NOR configuration with three input transistors Q ₁ , Q ₂ , and Q ₃ , and the output buffer has one transistor. An example is shown for the case of a non-inverting output configuration with an input transistor Q ₁₁ . Q ₄ is an internal gate reference transistor with a reference voltage V _BB applied to its base;
_Q5 is an internal gate emitter follower transistor, with an emitter follower resistor on the emitter.
R ₄ is connected and the emitter is output. _R1 , _R2
are load resistors connected to the collectors of the input transistors Q ₁ , Q ₂ , Q ₃ and the collector of the reference transistor Q ₄ , respectively, and R ₃ is a load resistor connected to the collectors of the input transistors Q ₁ , Q ₂ , Q 3 and the reference transistor Q ₃ . This is a resistor connected to the emitter of the lens transistor _Q4 . Further, Q ₁₄ and Q ₁₅ are reference transistors and emitter follower transistors of the output buffer, respectively, R ₁₁ and R ₁₂ are load resistors, and R ₁₃ is the emitter of the input transistor Q ₁₁ and the reference transistor Q ₁₄ . _R14 is an emitter follower resistor for the output buffer and may be added externally. Furthermore, l ₁ , l ₂ , and l ₃ are input terminals of the internal gate, O ₁ is an output terminal of the internal gate, and l ₁₁ and O ₁₁ are the input terminal and output terminal of the output buffer, respectively. V _CC is normally set to ground potential, and V _EE is given a negative potential. In such a configuration, the output buffer is usually driven by an internal gate, so that the output terminal O ₁ of the internal gate and the input terminal L ₁₁ of the output buffer
is connected.

By the way, in a typical gate array type master slice LSI, in order to achieve as high speed and low power consumption as possible, the circuit elements that make up the internal gates are miniaturized to reduce stray capacitance and operate with a small current. On the other hand, since the output buffer needs to sufficiently drive a large external capacitance, the circuit current cannot be reduced much, and the current value is set to be larger than that of the internal gate. For this reason, since the output buffer is composed of transistors having a larger size than the internal gate, the equivalent input capacitance of the output buffer becomes large. In addition, as shown in the configuration diagram of FIG.
Since the output buffer is arranged around the chip, the wiring between the output buffer and the internal gate becomes long, and the wiring capacitance tends to increase. Therefore, when the output buffer is driven by an internal gate, the load capacitance becomes large and the delay time, especially the delay time at the rise of the output, becomes large. Moreover, when a plurality of output buffers are driven by one internal gate, the delay time increases further.

As described above, the gate array type master slice LSI configured with the conventional ECL circuit has the disadvantage that the delay time of the internal gate that drives the output buffer becomes large.

The present invention was made to eliminate the above-mentioned drawbacks of the conventional device, and aims to improve the delay time by increasing the driving capability of the internal gate for driving the output buffer against the load capacitance. This invention will be explained in detail below.

FIG. 3 is a circuit diagram showing an embodiment of a large-scale integrated circuit device according to the present invention. In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts. Also, _R15
is a resistor newly inserted between the input terminal of the output buffer and the power supply voltage _VEE .

If the configuration is as shown in Figure 3, the output buffer B
Since resistors _R4 and _R15 are connected in parallel to the internal gate emitter follower transistor _Q5 that drives the emitter follower transistor Q5, the equivalent emitter follower resistance becomes small. Therefore, the drive capability of the internal gate with respect to the load capacitance is increased, and the delay time is improved. In other words, the delay time t _PHL at the time of falling of the emitter follower circuit is determined by the resistance value R _ef of the resistor connected to the emitter of the emitter follower transistor Q ₅ and the load capacitance.
For C _L , there is the following relationship.

t _PHL ∝R _ef・C _L ...( ₁ ) In the above embodiment, the ( _1st By making the resistor R _ef in the equation ) smaller, it is possible to improve the delay time when the output of the internal gate falls.

FIG. 4 shows a configuration diagram when one internal gate drives a plurality of output buffers. In the figure, B ₁ ,
B ₂ ,...,B _o represents n output buffers,
R ₁₅ , R ₂₅ , . . . , R _o5 are resistors added to the input ends of the respective output buffers, and are set to the same resistance value. By configuring a configuration in which a resistor whose resistance value is always set to the same value is always added to the input terminal of the output buffer, the delay time can be greatly improved when driving multiple output buffers with one internal gate. can do. That is, the equivalent input capacitance of the output buffer is _Cio , and the resistance values of the emitter follower resistor _R4 of the internal gate and the resistors added to the input terminal of each output buffer are all _R0 ,
If the wiring capacitance is _CM , then R _ef · _CL in equation (1) becomes as follows.

R _ef ·C _L =R ₀ /n+1(nC _io +C _M )...(2) On the other hand, according to the conventional circuit configuration, the following occurs.

R _ef · C _L = R ₀ (nC _io + C _M ) ...(3) As is clear from comparing equations (2) and (3), according to the present invention, compared to the conventional circuit configuration, As a result, the delay time when the output falls can be significantly improved, and at the same time, the difference in delay time of the internal gates depending on the number of output buffers driven by the internal gates can be significantly reduced. In other words, a resistor pattern is formed in the master pattern forming area of each output buffer, and when using the output buffer,
By always adding a resistor to the input end of the output buffer, the delay time of the internal gate that drives the output buffer can be improved.

However, with this configuration, when driving multiple output buffers with one internal gate, many resistors are added in parallel, so the current flowing through the emitter follower transistor of the internal gate increases. do. However, since the transistors that make up the internal gates are formed in a small size to accommodate the minute operating current, when a large current flows through them, the output level drops significantly, causing the problem that the desired operation cannot be achieved. . In such a case, the number of resistors added in parallel may be limited to limit the current flowing through the emitter follower transistor.

FIG. 5 is a diagram showing an embodiment in which the number of resistors to be added is limited. By adding resistors R ₁₅ and R ₂₅ only to the input ends of output buffers B ₁ and B ₂ and not adding resistors to the input ends of output buffers B ₃ to _{B o} , the internal gate The current flowing through the emitter follower transistor can be limited. In other words, a master pattern is formed in advance so that two different types of output buffers can be configured by changing only the wiring pattern: an output buffer with a resistor added to the input end and an output buffer without a resistor added to the input end. If the internal gate drives a large number of output buffers, the desired output buffer can be achieved by appropriately selecting two types of output buffers and limiting the number of resistors added to the input terminal of the output buffer. The delay time of internal gates can be improved while ensuring operation.

Note that in the above embodiment, only the case of an output buffer with one input and non-inverting output was explained.
It may be an inverted output format or a multi-input format, and the same effects as the above embodiments can be obtained.

As explained in detail above, this invention
In a gate array type master slice LSI consisting of an ECL circuit, a resistor can be added between the input terminal of the output buffer and the power supply V _EE line, so the delay time of the internal gate that drives the output buffer can be reduced. There are advantages that can be improved.

[Brief explanation of the drawing]

Figure 1 is a gate array type master slice LSI
2 is a circuit diagram showing a logic circuit device with a conventional ECL circuit configuration, FIG. 3 is a circuit diagram showing an embodiment of a large-scale integrated circuit device according to the present invention, and FIG. and FIG. 5 are configuration diagrams showing other embodiments of the large-scale integrated circuit device according to the present invention. In the figure, 101 to 104 are master pattern forming regions for internal gates, 111 to 114 are master pattern forming regions for input buffers or output buffers, Q ₁ , Q ₂ and Q ₃ are input transistors for internal gates, and Q ₄ is a reference transistor for the internal gate, _Q5 is an emitter follower transistor for the internal gate, _R1 , _R2 is a load resistor for the internal gate, _R3 is a resistor for the internal gate,
_R4 is the emitter follower resistor for the internal gate,
Q ₁₁ is the input transistor for the output buffer, Q ₁₄
is a reference transistor for output buffer,
Q ₁₅ is the emitter follower transistor for the output buffer, R ₁₁ and R ₁₂ are the load resistors for the output buffer, R ₁₃ is the resistor for the output buffer, R ₁₄ is the emitter follower resistor for the output buffer, and R ₁₅ ，
R ₂₅ , R ₃₅ and R _o5 are resistors selectively added to the input terminal of the output buffer, A is an internal gate, B,
B ₁ , B ₂ , B ₃ and B _o are the output buffers, l ₁ , l ₂ and l ₃ are the input terminals of the internal gate, O ₁ is the output terminal of the internal gate, l ₁₁ , l ₂₁ , l ₃₁ and l _o1 is the input terminal of the output buffer, and _O11 is the output terminal of the output buffer. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Gate array type master slice integration in which various logic circuits are constructed by forming circuit elements such as transistors and resistors in advance by using all pre-wiring processes in common and changing only the wiring process. In a circuit having a plurality of internal gates and a plurality of output buffers configured of an emitter-coupled logic circuit having at least one input transistor, there is a selective connection between the input terminal of the output buffer and the power supply line. 1. A large-scale integrated circuit device, characterized in that at least one resistor can be added to the circuit through a wiring process. 2 At least one resistor having the same or similar value as the resistor connected to the emitter of the emitter follower transistor of the emitter-coupled logic circuit that constitutes the internal gate between the input end of the output buffer and the power supply line is installed in the wiring process. 2. The large-scale integrated circuit device according to claim 1, wherein more than one circuit can be selectively added. 3. The large-scale integrated circuit device according to claim 1 or 2, characterized in that one resistor is always added between the input end of the output buffer and the power supply line. 4. When a plurality of output buffers are driven by the same internal gate, the number of resistors connected in parallel between the commonly connected input terminals of the output buffers and the power supply line is limited to a predetermined number. A large-scale integrated circuit device according to claim 1 or 2.