JPS6157530U - - Google Patents

Info

Publication number
JPS6157530U
JPS6157530U JP1984141306U JP14130684U JPS6157530U JP S6157530 U JPS6157530 U JP S6157530U JP 1984141306 U JP1984141306 U JP 1984141306U JP 14130684 U JP14130684 U JP 14130684U JP S6157530 U JPS6157530 U JP S6157530U
Authority
JP
Japan
Prior art keywords
groove
lead frame
semiconductor
molded block
resin molded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984141306U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984141306U priority Critical patent/JPS6157530U/ja
Publication of JPS6157530U publication Critical patent/JPS6157530U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図および第２図は本考案の実施例を示し、
第１図はこの実施例の一部切欠斜視図、第２図は
その縦断側面図、第３図は成型金型を示す縦断面
図、第４図は従来例を示す一部切欠平面図、第５
図はその側面図である。 １…半導体チツプ、２…リードフレーム、５…
リード端子、７…樹脂成型ブロツク、８…樹脂成
型ブロツクの外面、９…溝。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 半導体チツプと、金属製のリードフレーム
    とを備え、該リードフレームに形成された複数の
    リード端子をそれぞれ半導体チツプに接続すると
    ともに、該半導体チツプとリードフレームとを樹
    脂モールドにより一体にパツケージングしてなる
    半導体装置において、前記樹脂モールドにより形
    成された樹脂成型ブロツクの外面に、これの成型
    時に発生する内部応力を緩和する溝を形成したこ
    とを特徴とする半導体装置。 (2) 前記実用新案登録請求の範囲第１項に記載
    の半導体装置において、前記溝が前記樹脂成型ブ
    ロツクの上下両面に周回状に形成されている半導
    体装置。
JP1984141306U 1984-09-18 1984-09-18 Pending JPS6157530U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984141306U JPS6157530U (ja) 1984-09-18 1984-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984141306U JPS6157530U (ja) 1984-09-18 1984-09-18

Publications (1)

Publication Number Publication Date
JPS6157530U true JPS6157530U (ja) 1986-04-17

Family

ID=30699649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984141306U Pending JPS6157530U (ja) 1984-09-18 1984-09-18

Country Status (1)

Country Link
JP (1) JPS6157530U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460564A (en) * 1977-10-24 1979-05-16 Hitachi Ltd Resin mold semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460564A (en) * 1977-10-24 1979-05-16 Hitachi Ltd Resin mold semiconductor device

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