JPS6160516B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device, and particularly to a static storage device.
This relates to a RAM read control device.

Recently, microcomputers have been widely used as data processing systems, and they are used to process data in the system's built-in memory using instructions.
A RAM read controller is used. Conventional RAM read devices have both Q, which is the data common output line of RAM cells, and its inverted common output line, but only Q or Q is coupled to the read amplifier. . For this reason, ALU (Arithmetic Logic
Unit) is a data memory that processes data.
Once stored in RAM, the most common way to obtain the inverted data of a series of processed data is to specify the RAM address, read the data to the accumulator, invert it in ALU, and then Write to RAM, do this operation every time
It was necessary to execute the program while changing the RAM address specification.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device that can easily obtain inverted data of the memory.

According to the present invention, between a static RAM having a set/resettable flip-flop that stores a selection signal, and an output readout amplifier having an inverted output line thereof, the output line and the inverted output line are controlled by the selection signal. The device is characterized in that it includes a control gate, and by setting or resetting the flip-flop, the information stored in the static RAM and its inverted information can be arbitrarily selected.

Next, one embodiment of the present invention will be described with reference to FIG. Although this embodiment shows an example in which an N-channel MOS transistor is used, a P-channel MOS transistor is essentially the same.

In FIG. 1, memory cells C0 to _C3 are located at each intersection of word lines _A0 to _A3 , _a pair of output lines, and Q.
The memory cells C ₀ to _{C 3} have a pair of gates (A ₀ , A ₀ Q) and (A ₁ , A ₁ Q) whose control electrodes are connected to the word lines A ₀ to A ₃ , respectively. , (A ₂
, A ₂ Q) and (A ₃ , A ₃ Q) to the inverting common output line and the common output line Q. Here, as the memory cells _C0 to _C3 , memory cells that generate a true complement output signal of a flip-flop type are used, but any cell that generates a true complement output can be specified as a flip-flop type. isn't it. The common output line Q is generally called a date line.

Output line Q is transargate TSF ₂ and
Coupled to the input of sense amplifier RA via TSF ₁ . The true output of the control flip-flop FF is input to the transfer gate TSF ₂ .
The inverted output of the flip-flop FF is input to the transfer gate _TSF1 .

Generally, when writing data to RAM and reading data from RAM during data processing, a selection signal storage flip-flop is used.
Assuming that FF is set in the initial state of the system, the output of FF is high level, so gate TSF ₁ is non-conductive, and gate TSF ₂ is conductive, so all data processing is performed by RAM. This is executed via the data common line Q, that is, the digit line Q. Next, when inverted data of a series of data that has been processed and stored in RAM is required, the flip-flop FF is
By resetting, the output of FF becomes low level and the output of inverter INV becomes high level, so TSF ₂ becomes non-conductive and TSF ₁ becomes conductive, so the RAM data common line is output to the read amplifier. This means that all values at the specified RAM address can be treated as inverted information of the stored values. Therefore, by using the present invention, it is possible to reverse the stored information (pattern) with a single command in a video system, etc. that handles a large amount of data, and the burden on so-called software can be greatly reduced. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. C ₀ - C ₃ are static RAM cells, A ₀ - _{A 3} are address lines, Q is a RAM data common line, Q is an inverted data common line, A ₀ Q - _{A 3} Q are cells when each address is selected. A 0 to A 3 are selection gates that lead the data to the data common line, and A ₀ to _{A 3} are selection gates that lead the data to the inverted common line. RA is a read amplifier, FF is a flip-flop that stores a selection signal for outputting Q or not, R is its reset input, and S is its set input. TSF ₁ is a transfer gate that leads to RA,
TSF ₂ is a transfer gate that leads Q to RA. INV
is an inverter.

Claims (1)

[Claims] 1. A first digit line to which the true output of the memory is given, a second digit line to which the auxiliary output of the memory is given, a readout amplifier, and between the first digit line and the input of the readout amplifier. A first gate is provided, a second gate is provided between the second digit line and the input of the readout amplifier, one output is used as a control input of the first gate, and the other output is 2. A storage device comprising: a flip-flop having the second gate control input; and either a true output or an auxiliary output of the memory can be read depending on the state of the flip-flop.