JPS6178149A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6178149A
JPS6178149A JP59199563A JP19956384A JPS6178149A JP S6178149 A JPS6178149 A JP S6178149A JP 59199563 A JP59199563 A JP 59199563A JP 19956384 A JP19956384 A JP 19956384A JP S6178149 A JPS6178149 A JP S6178149A
Authority
JP
Japan
Prior art keywords
lead
hole
holes
inner part
diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59199563A
Other languages
Japanese (ja)
Inventor
Masachika Masuda
正親 増田
Akira Suzuki
明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59199563A priority Critical patent/JPS6178149A/en
Publication of JPS6178149A publication Critical patent/JPS6178149A/en
Priority to US07/159,902 priority patent/US4862246A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to improve the adhesive strength between the sealing medium and the inner part of the lead and the mechanical strength of the lead by a method wherein one piece or plural pieces of a hole or holes, a notch or notches or a penetrating hole or penetrating holes for lead fixation is/are provided in the inner part and the diameter thereof on the side of the bottom part of each hole or each penetrating hole for lead fixation is formed smaller than the diameter of the surface area of the hole or the penetrating hole. CONSTITUTION:The diameter phiB of the bottom part of a hole 11 for lead fixation provided in the surface or back surface of the inner part 10 of the lead is made smaller than the diameter phiA of the hole 11 on the side of the surface or back surface. Moreover, the diameter phiB of the bottom part of a penetrating hole 12 for lead fixation formed from both of the surface and back surface of the inner part 10 of the lead is made smaller than the diameter ALPHA of the hole 12 on the side of the surface of back surface. When the holes 11 are provided in the surface and back surface of the inner part 10 of the lead, the sealing medium flows in the holes 11 and the parts of the holes 11 are cured. As a result, the adhesive strength between the sealing medium and the inner part 10 of the lead and the mechanical strength of the lead are augmented. Moreover, when the holes 11 and the penetrating holes 12 are provided in combination with each other, the adhesive strength can be enhanced markedly.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置に係り、特に、半導体装置のパッ
ケージ技術に適用し、て有効な技術に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a packaging technique for a semiconductor device.

〔背景技術〕[Background technology]

大規模集積回路（ＬＳＩ）等の半導体チップを樹脂また
はガラスで封止した半導体装置等に用いられるリードに
、第１図（Ａ）、ＣＢ）に示すように。As shown in FIGS. 1A and 1B, leads are used in semiconductor devices such as large-scale integrated circuits (LSIs) sealed with resin or glass.

プレス技術により、リード１のインナー部に固定用貫通
孔（ロックホール）２を設け、封ＩＥ時における封止材
とリードｌとの境界面の接着強度を向上させて、リード
に外力又は温度サイクル等による応力（ストレス）が加
わって発生する亀裂や隙間からの水分の浸入を防止する
ことが考えられる。Using pressing technology, a fixing through hole (lock hole) 2 is provided in the inner part of the lead 1 to improve the adhesive strength at the interface between the sealing material and the lead 1 during sealing IE, and to prevent the lead from external force or temperature cycles. It is possible to prevent moisture from entering through cracks and gaps that occur when stress is applied.

しかしながら、近年、益々高集積度化が要求され、多リ
ード（多ピン）の半導体装置となってきているため、そ
れに用いられるリード１の幅は１ｍくなってきている。However, in recent years, there has been an increasing demand for higher integration, leading to multi-lead (multi-pin) semiconductor devices, and the width of the leads 1 used therein has become 1 m.

これは、特にフラットパックタイプパッケージ（Ｐ　Ｐ
　Ｐ）において顕著である。This is especially true for flat pack type packages (P
P) is notable.

このために前記固定用貫通孔２をプレス技術によりリー
ドエに設けると、リードｌの機械的強度が低下し、リー
ド１の外部からの応力や温度サイクルによる応力が加わ
ると、リード曲りや封止材とリードとの間に亀裂、隙間
等が発生することが。For this reason, if the fixing through hole 2 is provided in the lead edge by pressing technology, the mechanical strength of the lead l will be reduced, and if stress from the outside of the lead 1 or stress due to temperature cycles is applied, the lead may bend or the sealing material may bend. Cracks, gaps, etc. may occur between the lead and the lead.

発明者の検討の結果、明らかになった。This became clear as a result of the inventor's study.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、封止材とリードのインナー部との接着
強度及び機械的強度を向上させた耐湿性に優れた半導体
装〔を提供することにある。An object of the present invention is to provide a semiconductor device with excellent moisture resistance and improved adhesive strength and mechanical strength between a sealing material and an inner portion of a lead.

本発明の前記ならびにその他の目的と新規な特徴は、水
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち５代表的なものの概
要を説明すれば、下記のとおりである。A summary of five representative inventions among the inventions disclosed in this application is as follows.

すなわち、半導体装置のリードのパッケージに封止され
た部分（インナー部）に、リード固定用穴。In other words, there are holes for fixing the leads in the part (inner part) of the leads of the semiconductor device that are sealed in the package.

切り欠き（ノツチ）又は貫通孔を一個又は複数個設け、
該リード固定用穴又は貫通孔の底部側の径寸法を表面側
の径寸法よりも小さく形成する。これにより、パッケー
ジの封止材とリードのインナー部との接着強度及びリー
ドの機械的強度を、多リード型半導体装置においても、
向上させるようにしたものである。また、前記リード固
定用穴１貫通孔、切り欠き等を組合わせて設けることに
より。Provide one or more notches or through holes,
The diameter on the bottom side of the lead fixing hole or through hole is formed to be smaller than the diameter on the surface side. This improves the adhesive strength between the package encapsulant and the inner part of the leads, as well as the mechanical strength of the leads, even in multi-lead semiconductor devices.
It was designed to improve the performance. Further, by providing a combination of the lead fixing hole 1 through hole, notch, etc.

さらに、封止材とリードのインナー部との接着強度及び
機械的強度を向上させたものである。Furthermore, the adhesive strength and mechanical strength between the sealing material and the inner portion of the lead are improved.

以下１本発明の構成について、実施例とともに説明する
。The configuration of the present invention will be explained below along with examples.

なお９本発明の詳細な説明するための図面において、同
一の機能を有するものは同一符号を付け、その繰り返し
の説明は省略する。9. In the drawings for detailed explanation of the present invention, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

〔実施例■〕[Example ■]

第１図（Ａ）乃至（Ｄ）及び第２図（Ａ）乃至（Ｃ）は
。Figures 1 (A) to (D) and Figures 2 (A) to (C).

本発明の実施例Ｉの半導体ｖＡｗｃ用リードの構成を説
明するための図である。第１図（Ａ）乃至（Ｄ）はその
リードの要部の断面拡大図、第２図（Ａ）は第２図に示
す要部を複数個設けた平面図、第２図（Ｂ）、（Ｃ）は
第２図（Ａ）の１−１切断線における断面図である。FIG. 2 is a diagram for explaining the configuration of a semiconductor vAwc lead according to Example I of the present invention. Figures 1 (A) to (D) are enlarged cross-sectional views of the main parts of the lead, Figure 2 (A) is a plan view showing a plurality of the main parts shown in Figure 2, Figure 2 (B), (C) is a sectional view taken along the line 1-1 in FIG. 2(A).

第１図（Ａ）乃至（Ｄ）及び第２図（Ａ）乃至（Ｃ）に
おいて、１０はリードのインナー部、１１は前記リード
のインナー部１０の表面又は裏面に設けられたリード固
定用穴（以下、単に、穴という）であり、その底部の径
φＢがその表面側又は裏面側の径φＡよりも小さくなっ
ている（φＢくφＡ）。この穴１１は１等方性のエツチ
ング技術によって形成される。１２はリードのインナー
部の両面からエツチング技術によって形成されたリード
固定用貫通孔（以下、単に１貫通孔という）であり、そ
の底部の径φＢがその表面側又は裏面側の径φＡよりも
小さくなっている（φＢ〈φＡ）、この穴１１は、等方
性のエツチング技術によって形成される。In FIGS. 1(A) to (D) and FIGS. 2(A) to (C), 10 is the inner part of the lead, and 11 is a lead fixing hole provided on the front or back surface of the inner part 10 of the lead. (hereinafter simply referred to as a hole), and the diameter φB at the bottom thereof is smaller than the diameter φA at the front side or the back side (φB × φA). This hole 11 is formed by an isotropic etching technique. 12 is a lead fixing through hole (hereinafter simply referred to as 1 through hole) formed by etching technology from both sides of the inner part of the lead, and the diameter φB at the bottom is smaller than the diameter φA on the front side or the back side. (φB<φA), this hole 11 is formed by an isotropic etching technique.

そして、前記穴１１を、例えば、第２図（Ｂ）に示すよ
うに、リードのインナー部１０の両面に設けることによ
り、エポキシレジン等の封止材（図示していない）が穴
１１に流れ込んで硬化されるので、封止材とリードのイ
ンナー部１０との接着強度及び機械的強度が増大する。By providing the holes 11 on both sides of the inner part 10 of the lead, for example, as shown in FIG. 2(B), a sealing material such as epoxy resin (not shown) flows into the holes 11. Since the sealing material is cured, the adhesive strength and mechanical strength between the sealing material and the inner portion 10 of the lead are increased.

また、例えば、第３図（Ｃ）に示すように、前記穴及び
貫通孔を組合わせて設けることにより、前記と同様の作
用で同等の機械的強度を保持し、かつ、より一層の接着
強度を増大させることができる０貫通孔１２に封止材が
流れ込み硬化すると、封止材とリードとの接着強度は穴
１１を用いたときより極めて大きい。For example, as shown in FIG. 3(C), by providing the holes and through holes in combination, the same mechanical strength can be maintained through the same effect as described above, and even higher adhesive strength can be achieved. When the sealant flows into the through hole 12 and hardens, the adhesive strength between the sealant and the lead is much greater than when the hole 11 is used.

穴１１または貫通孔１２を設けても、リード１０の強度
はあまり低下しない、穴１１または貫通孔１２は、その
直径かり一に表面より穴１１の底または貫通孔１２の中
央で小さくなるように形成されているためである。この
ために１等方性エツチングによって、穴１１および貫通
孔１２が形成される。また、エツチング技術を用いるこ
とによって、＊騙なリードへの加工が可能となる。Even if the hole 11 or the through hole 12 is provided, the strength of the lead 10 is not significantly reduced. This is because it is formed. For this purpose, holes 11 and through holes 12 are formed by isotropic etching. In addition, by using etching technology, it is possible to create *deceptive leads.

貫通孔１２を設けたリードは、第１図（Ｃ）のようなリ
ードよりも、強度が多少小さくなる程度である。第２図
（Ｃ）のように、六１１と貫通孔１２とを交互に設けた
場合のリード１０の全体としての強度は、穴１１のみを
設けた場合と殆んど変わりがない。The strength of the lead provided with the through hole 12 is somewhat smaller than that of the lead shown in FIG. 1(C). As shown in FIG. 2(C), the overall strength of the lead 10 when the holes 11 and through holes 12 are provided alternately is almost the same as when only the holes 11 are provided.

〔実施例■〕[Example ■]

第３図は１本発明の実施例■のＰＰＰ型半導体装置用リ
ードフレームの構成を説明するための図であり、第４図
（Δ）乃ｆｆ１（Ｄ）は１本実施例Ｉに用いられるリー
ドフレームの要部の拡大斜視図である。FIG. 3 is a diagram for explaining the structure of a lead frame for a PPP type semiconductor device according to Embodiment 2 of the present invention, and FIG. 4 (Δ) to ff1 (D) are used for Embodiment I FIG. 3 is an enlarged perspective view of main parts of the lead frame.

第３図において、１３は半導体チップを塔載する方形の
タブ、１４はタブ１３の四角に接続するタブ吊リード、
１５は切り欠き、１６はタイバー。In FIG. 3, 13 is a rectangular tab on which a semiconductor chip is mounted, 14 is a tab suspension lead connected to the square of the tab 13,
15 is a notch, 16 is a tie bar.

１７はリードの７ウタ一部である０図中の点線は。17 is part of the 7th part of the lead.0 The dotted line in the figure is.

このリードフレームを封止した際に、樹脂又はガラス等
の封止材によって覆われる領域を示す。It shows the area covered by a sealing material such as resin or glass when the lead frame is sealed.

本実施例■の半導体装置用リード部は、第３図に示すよ
うに、多数の幅の狭いリードが配設されている。このリ
ードのインナー部ｌＯおよびタブ吊りリード１４には、
前述の第１図（Ａ）乃至（Ｄ）に示す穴１１．貫通孔１
２及び第４図（Ａ）乃至（Ｄ）に示すような切り欠き１
５をそれぞれ適当に組合わせて設けている。As shown in FIG. 3, the semiconductor device lead portion of this embodiment (2) is provided with a large number of narrow leads. The inner part lO of this lead and the tab hanging lead 14 include:
Hole 11 shown in FIGS. 1(A) to 1(D) above. Through hole 1
2 and a cutout 1 as shown in FIGS. 4(A) to (D)
5 are provided in appropriate combinations.

このように構成することにより、封止材がリードのイン
ナー部１０の表裏及び左右の凹部に流れ込んで硬化する
ので、リードのインナー部１０は上下左右の４方向で固
定され、リードと封止部との接着強度がより一層増大す
る。With this configuration, the sealing material flows into the front, back, left and right recesses of the inner part 10 of the lead and hardens, so the inner part 10 of the lead is fixed in four directions (up, down, left and right), and the lead and the sealing part are fixed. This further increases the adhesive strength.

〔実施例■〕[Example ■]

本発明の実施例■は、第５図に示すように、前記実施例
■の機械的強度が特に必要なリードのインナー部１０Ａ
には１例えば、切り欠き１５を設けないようにしたもの
である。すなわち、タブ吊りリード１４Ａおよびこの近
傍の複数本のインナーリードＩＯＡには、穴１１又は貫
通孔１２のみが設けられる。Embodiment (2) of the present invention, as shown in FIG.
1, for example, the notch 15 is not provided. That is, only the hole 11 or the through hole 12 is provided in the tab suspension lead 14A and the plurality of inner leads IOA in the vicinity thereof.

ＦＰＰ型半導体装置の封止をするとき、モールド用の上
下の金型内のキャビティに、樹脂がゲートから注入され
る。樹脂の注入は１図中矢印方向に行なわれる。ゲート
近傍のリードには注入される樹脂の圧力が働く、このた
め、他のり一層１０より大きい強度が必要とされる。When sealing an FPP semiconductor device, resin is injected into cavities in upper and lower molds through the gate. The resin is injected in the direction of the arrow in FIG. The pressure of the injected resin acts on the leads near the gate, so the strength is required to be greater than that of the other layers.

このように、必要に応じてリードのインナー部１０及び
ＩＯＡに設ける前記穴１１．貫通孔１２及び切り欠き１
５を選択して設けることにより、より適切なリードの取
り付けができるので、半導体装置の信頼性の向上及び長
寿命化がはかれる。In this way, the holes 11 are provided in the inner part 10 of the lead and the IOA as necessary. Through hole 12 and notch 1
By selecting and providing 5, it is possible to attach the leads more appropriately, thereby improving the reliability and extending the life of the semiconductor device.

〔効果〕〔effect〕

以上説明したように、本願で開示した新規な技術手段に
よれば、次のような効果を得ることができる。As explained above, according to the novel technical means disclosed in this application, the following effects can be obtained.

（１）半導体装置用リードのインナー部に、リード固定
用穴又は貫通孔を一個又は複数個設け、該リード固定用
穴又は貫通孔の底部側の径寸法を表面側の径寸法よりも
小さくすることにより、細いリードにおいても、リード
の機械的強度を低下させることなく、封止材とリードの
インナー部との接着強度を向上させることができる。(1) One or more lead fixing holes or through holes are provided in the inner part of the lead for semiconductor devices, and the diameter on the bottom side of the lead fixing hole or through hole is smaller than the diameter on the surface side. As a result, even in the case of thin leads, the adhesive strength between the sealing material and the inner portion of the leads can be improved without reducing the mechanical strength of the leads.

（２）エツチングにより前記穴又は貫通孔を形成するの
で０幅の微綱なリードにも容易に形成でき、リードの機
械的強度を低下させない。(2) Since the hole or through-hole is formed by etching, it can be easily formed even in a zero-width, fine-wire lead, and does not reduce the mechanical strength of the lead.

（３）等方性エツチングにより前記穴又は貫通孔を形成
するので、容易に底部側の直径を表面側より小さくでき
る。(3) Since the holes or through holes are formed by isotropic etching, the diameter on the bottom side can be easily made smaller than on the surface side.

（４）貫通孔の形状を第１図（Ｄ）のようにすることに
より、リードの機械的強度をあまり低下させずに、リー
ドと封止材との接着強度を大きくできる。(4) By configuring the shape of the through hole as shown in FIG. 1(D), the adhesive strength between the lead and the sealing material can be increased without reducing the mechanical strength of the lead too much.

（５）前記穴、Ｊ￥過通孔び切り欠きを適当に選択し、
それらを組合わせて設けることにより、さらに、封止材
とリードのインナー部との接着強度及び機械的強度を増
大させることができる。(5) Appropriately select the hole, J\ through hole and notch,
By providing them in combination, it is possible to further increase the adhesive strength and mechanical strength between the sealing material and the inner portion of the lead.

（６）前記穴と貫通孔を１本のリードに交互に設けるこ
とにより、そのリードの機械的強度を低下させることな
く、リードと封止材との接着強度を向上できる。(6) By alternately providing the holes and through holes in one lead, the adhesive strength between the lead and the sealing material can be improved without reducing the mechanical strength of the lead.

（７）樹脂の注入されるゲート近傍のリードの機械的強
度を他のリードよりも強くすることによって、樹脂封止
の際のリードの変形を防止できる。(7) By making the mechanical strength of the lead near the gate into which resin is injected stronger than that of other leads, deformation of the lead during resin sealing can be prevented.

（８）　　Ｆｐｐ！！：１半導体装置の如く、リード幅
の小さい半導体装置においてもその信頼性を高くするこ
とができる。(8) Fpp! ! The reliability of a semiconductor device with a small lead width, such as a :1 semiconductor device, can be improved.

（９）リードに外部からの応力や温度サイクルによる応
力が加わっても、リード曲り、リード抜けや封止部の亀
裂発生を防止することができるので。(9) Even if external stress or stress due to temperature cycles is applied to the leads, it is possible to prevent lead bending, lead disconnection, and cracking of the sealing part.

半導体装置の信頼性の向上及び長寿命化をはかることが
できる。It is possible to improve the reliability and extend the life of the semiconductor device.

以上１本発明を実施例にもとずき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
はいうまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

例えば、前記穴２貫通孔、切り火きを設けるリード位置
は、前記実施例に限定されるものでなく、必要に応じて
選択すればよい。また１本発明は。For example, the hole 2 through-hole and the lead position where the cutoff is provided are not limited to those in the embodiments described above, and may be selected as necessary. Another invention is this.

樹脂封止型半導体装置以外の半導体装置、例えば。Semiconductor devices other than resin-sealed semiconductor devices, for example.

ガラス封止型半導体装置にも使用できることは言うまで
もない。Needless to say, it can also be used in glass-sealed semiconductor devices.

【図面の簡単な説明】 第１図（Ａ）乃至（Ｄ）及び第２図（Ａ）乃至（Ｃ）は
。 本発明の実施例１の半導体装置用リードの構成を説明す
るための図であり、第１図（Ａ）乃至（Ｄ）ｉよそのリ
ードの要部の断面拡大図、第２０は、第１図に示す要部
を複数個設けた平面図及びＩ−１切断線における断面図
、 第３図は１本発明の実施例■の半導体装置用リード部の
構成を説明するための平面図。 第４図（Ａ）乃至（１つ）は、前記実施例■に用し）ら
れるリード要部の拡大斜視図、 第５図は、本発明の実施例■の半導体装置用リード部の
構成を説明するための平面図、第６図（Ａ）、（８）は
、封止型半導体装置に用いられるリードの問題点を説明
するための平面及び断面図である。 図中、１０．ＩＯＡ・・・リードのインナ部、１１・・
・リード固定用穴、１２・・リード固定用貫通孔、１３
・・・タブ、１４・・・タブ吊リード、１５・・切り欠
きである。 「″ ＼　　　　　　　　　　　　　　　　　へ′ヅ 第　　　４　　図 （Ａ）　　　　　　　　　　　　　　　　　　　　（ｃ
ン（Ｓ）（Ｄ） 第　　６　　図[Brief Description of the Drawings] Figures 1 (A) to (D) and Figures 2 (A) to (C). 20 is a diagram for explaining the configuration of a lead for a semiconductor device according to Example 1 of the present invention, and FIG. FIG. 3 is a plan view showing a plurality of essential parts shown in the figure and a sectional view taken along the cutting line I-1; FIG. FIGS. 4(A) to (1) are enlarged perspective views of the main parts of the lead used in the embodiment (2), and FIG. FIGS. 6(A) and 6(8) are plan views and cross-sectional views for explaining problems with leads used in sealed semiconductor devices. In the figure, 10. IOA...Inner part of lead, 11...
・Hole for lead fixation, 12...Through hole for lead fixation, 13
...Tab, 14...Tab hanging lead, 15...Notch. ``'' ＼ へ'ㅅFig.
(S) (D) Figure 6

Claims (1)

【特許請求の範囲】 １、半導体装置用リードのインナー部に、リード固定用
穴又は貫通孔を有する半導体装置用リードであって、前
記リード固定用穴又は貫通孔の底部側の径寸法が表面側
の径寸法よりも小さいことを特徴とする半導体装置用リ
ード。 ２、前記リード固定用穴又は貫通孔をリードの表裏両面
からエッチング技術により形成したことを特徴とする特
許請求の範囲第１項記載の半導体装置用リード。 ３、前記リード固定用穴又は貫通孔をリードのインナー
部の長手方向に複数個設けたことを特徴とする特許請求
の範囲第１項記載の半導体装置用リード。 ４、前記リード固定用穴、貫通孔及び切り欠き部をリー
ドのインナー部の長手方向に、それぞれを組合わせて設
けたことを特徴とする特許請求の範囲第１項乃至第３項
のいずれかに記載の半導体装置用リード。 ５、前記特許請求の範囲第１項乃至第４項記載の半導体
装置用リードを用いたことを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device lead having a lead fixing hole or a through hole in the inner part of the semiconductor device lead, wherein the diameter of the bottom side of the lead fixing hole or through hole is on the surface. A semiconductor device lead characterized by having a diameter smaller than the side diameter. 2. The lead for a semiconductor device according to claim 1, wherein the lead fixing hole or through hole is formed by etching technology from both the front and back sides of the lead. 3. The lead for a semiconductor device according to claim 1, wherein a plurality of the lead fixing holes or through holes are provided in the longitudinal direction of the inner portion of the lead. 4. Any one of claims 1 to 3, characterized in that the lead fixing hole, the through hole, and the notch are provided in combination in the longitudinal direction of the inner part of the lead. A lead for semiconductor devices described in . 5. A semiconductor device characterized by using the lead for a semiconductor device according to any one of claims 1 to 4.
JP59199563A 1984-09-26 1984-09-26 Semiconductor device Pending JPS6178149A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59199563A JPS6178149A (en) 1984-09-26 1984-09-26 Semiconductor device
US07/159,902 US4862246A (en) 1984-09-26 1988-02-24 Semiconductor device lead frame with etched through holes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59199563A JPS6178149A (en) 1984-09-26 1984-09-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6178149A true JPS6178149A (en) 1986-04-21

Family

ID=16409905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59199563A Pending JPS6178149A (en) 1984-09-26 1984-09-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6178149A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226548A (en) * 1991-11-27 1993-09-03 Samsung Electron Co Ltd Lead frame for semiconductor device
US5258331A (en) * 1989-10-20 1993-11-02 Texas Instruments Incorporated Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars
JP2005217452A (en) * 2002-04-01 2005-08-11 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2009135379A (en) * 2007-11-29 2009-06-18 Seoul Semiconductor Co Ltd Moisture-proof LED package
JP2011066144A (en) * 2009-09-16 2011-03-31 Dainippon Printing Co Ltd Lead frame or substrate for led, semiconductor device, and method for manufacturing lead frame or substrate for led
JP2018064062A (en) * 2016-10-14 2018-04-19 大日本印刷株式会社 Lead frame and semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258331A (en) * 1989-10-20 1993-11-02 Texas Instruments Incorporated Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars
JPH05226548A (en) * 1991-11-27 1993-09-03 Samsung Electron Co Ltd Lead frame for semiconductor device
JP2005217452A (en) * 2002-04-01 2005-08-11 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2009135379A (en) * 2007-11-29 2009-06-18 Seoul Semiconductor Co Ltd Moisture-proof LED package
JP2011066144A (en) * 2009-09-16 2011-03-31 Dainippon Printing Co Ltd Lead frame or substrate for led, semiconductor device, and method for manufacturing lead frame or substrate for led
JP2018064062A (en) * 2016-10-14 2018-04-19 大日本印刷株式会社 Lead frame and semiconductor device

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