JPS6180823A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6180823A
JPS6180823A JP59201526A JP20152684A JPS6180823A JP S6180823 A JPS6180823 A JP S6180823A JP 59201526 A JP59201526 A JP 59201526A JP 20152684 A JP20152684 A JP 20152684A JP S6180823 A JPS6180823 A JP S6180823A
Authority
JP
Japan
Prior art keywords
light
etching
wafer
wavelength
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59201526A
Other languages
Japanese (ja)
Inventor
Makoto Sekine
誠 関根
Haruo Okano
晴雄 岡野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59201526A priority Critical patent/JPS6180823A/en
Publication of JPS6180823A publication Critical patent/JPS6180823A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain the manufacturing method for the semiconductor device to be processes at a low temperature having few damage caused by the projection of light by a method wherein the light directly made to irradiate at least on a sample, in the process to be performed after a prescribed light projecting process is conducted, is brought in the specific wavelength or above. CONSTITUTION:When an etching is going to be performed on a protective film BPSG18, a wafer is arranged in reactive gas, the purpose of etching is easily accomplished by projecting a condensed light at the part to be etched. However, the wavelength of the light to be projected at least on the wafer directly is set at 200nm or above, and an etching is accomplished without forming the center of electron capture on a gate oxide film 11. On the other hand, when Al is going to be deposited, a light (ArF laser beam) with which trimethylaluminum will be decomposed is made to irradiate in parallel with the wafer, and a laser having the wavelength of 200nm or more such a XeCl laser beam (308nm) is convergingly made to irradiate on the wafer, and Al is deposited.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は光化学反応を利用した半辱本装道の製造方法l
こ関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a method for producing hangihonsodo using photochemical reactions.
Regarding this.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

近年、、集積回路は微細化の一途を辿り、最近では最小
パターン寸法が1〜2〔μm〕の超LSIも試作開発さ
れるに至っている。このような政綱加工、例えばエツチ
ングの工程では反応性イオンエッチング( React
ive Ion Etching; R I E ) 
カ主流の技術であり、また?4膜堆I4の工程では低温
化プロセスに整合したイオンブレーティング法やプラズ
マCVD法等が広く用いられている。しかし、これらの
技術はいずれもプラズマを利用したプロセスであり,ゲ
ート醗化膜の破壊現象(吉日。
In recent years, integrated circuits have been increasingly miniaturized, and recently, prototypes of ultra-LSIs with a minimum pattern size of 1 to 2 [μm] have been developed. For example, in the etching process, reactive ion etching (React
ive Ion Etching; RIE)
Is it mainstream technology? In the process of the four-film stack I4, ion blating methods, plasma CVD methods, and the like, which are compatible with low-temperature processes, are widely used. However, all of these technologies are processes that use plasma, and the phenomenon of destruction of the gate oxide film (happy day) occurs.

渡辺;第5回ドライプロセスシンポジウム予稿渠。Watanabe: Proceedings of the 5th Dry Process Symposium.

4気学会,東京,1983)4の素子への照射損傷が懸
念され始めているのが現状である。
At present, there is a growing concern about radiation damage to the elements described in 4.4 Ki Gakkai, Tokyo, 1983).

以上のようなプラズマプロセスに対して荷電粒子を用い
ない無照射損傷のプロセスとして、取返光化学反応を利
用した薄膜堆積、エツチング、不dd吻拡散等の研究が
盛んに行われている。この光励起プロセスは、現在の他
のプロセスでは困難なマスクレス或いは選択堆積、エツ
チング、不純物ドーピング、酸化等の寅プロセスが可能
であり。
As a non-irradiation damage process that does not use charged particles in contrast to the above-described plasma process, research is being actively conducted on thin film deposition, etching, non-irradiation diffusion, etc. using reversal photochemical reactions. This photoexcitation process enables maskless or selective deposition, etching, impurity doping, oxidation, and other processes that are difficult with other current processes.

且つ木實的に低温プロセスであるため、将来のサブミク
ロンデバイスの侯逍プロセスにも十分整合すると考えら
れている。
In addition, since it is actually a low-temperature process, it is thought to be fully compatible with future processes for submicron devices.

この元プロセスにおいても、e、細化の進展に伴い、選
択的に光を照射し、エツチング、堆積、ドーピング等を
行う場合、高分解能を得るためζこきわめて短波長の光
を用いることが考えられる。元プロセスが照射損11y
Jを超さない理由として荷電粒子を用いないことの他に
、光のエネルギーが数eV以下と非常に低いことがあげ
られる。そのため将来遠紫外、真空紫外あるいはX線等
の高エネルギー線を用いた場合には照射損傷の発生が懸
;よされる。
Even in this original process, with the progress of thinning, when selectively irradiating light to perform etching, deposition, doping, etc., it is considered to use light with an extremely short wavelength to obtain high resolution. It will be done. The original process has an irradiation loss of 11y.
The reason for not exceeding J is that in addition to not using charged particles, the energy of light is very low, at several eV or less. Therefore, if high-energy rays such as deep ultraviolet, vacuum ultraviolet, or X-rays are used in the future, there is a risk of irradiation damage occurring.

〔発明の目的〕[Purpose of the invention]

本発明は以上の点に鑑みなされたものでその目的は光を
利用した照射損傷が少なくかつ低温プロセスの半専木装
置の製造方法を提供すること(こある。
The present invention has been made in view of the above points, and its object is to provide a method for manufacturing a semi-specialized wood device using light, which causes less damage due to irradiation and which is a low temperature process.

〔発明UJ概要〕[Overview of invention UJ]

本発明の骨子は光照射により″P廊本咲1表mlにエツ
チング、堆積等の処理を施した麦の1楓で800℃以上
の高温アニールが不可能である場合半導体装置表面に照
射される光は波長2QQnm以上の光を用い低温のアニ
ールでは回復しな−い照射損傷を防止することにある。
The gist of the present invention is to use light irradiation to irradiate the surface of a semiconductor device when high temperature annealing of 800°C or higher is not possible with one maple of wheat that has been subjected to etching, deposition, etc. The purpose of the light is to use light with a wavelength of 2QQnm or more to prevent radiation damage that cannot be recovered by low-temperature annealing.

〔発明の効果〕〔Effect of the invention〕

本発明によれば低温アニールでは回復しない高エネルギ
ーフォトンあるいは高エネルギー線に匙因すると考えら
れるシリコン酸化膜中の照射損メ  1の発生をなくシ
、半導体プロセスの無照射損μ。
According to the present invention, it is possible to eliminate the irradiation loss μ in the silicon oxide film that is thought to be caused by high-energy photons or high-energy rays that cannot be recovered by low-temperature annealing, and to reduce the non-irradiation loss μ in the semiconductor process.

低温プロセス化に望めて有効である。It is expected to be effective for low-temperature processing.

〔発明の実施例〕[Embodiments of the invention]

まず本発明の基礎となった実験結果ζこついて説明する
。近年MO8,デバイスの高集積化は微細寸法化(こよ
り進めらn−一方使用される電源電圧は自足させておき
たいという安望がある。そのためデバイスに加えられる
d気的ストレスは厳しくなり新たな1司榎がン白生じて
くる。その1つにホットエレクトロン効果がある。ざら
iこば細化の手段として′−子ビーム、 X 、hj(
リングラフィ、ドライプロセスがありこれらに含まれる
高エネルギー粒子は酸化膜に損傷を与えホットエレクト
ロン注入に伴ない硬化;1りでの屯荷捕嗅現象力5増大
しデバイスの信頼性を低下させる。M OS F E 
Tの物作中にドレイン近1労の空乏1凸で発生したホッ
トエレクトロンは、1(1jえば、5i−8iQ2の界
面障壁を越え得るエネルギーを高”i界より14でゲー
ト酸化膜中を流れてゲート・戎流を生ずる。そしてゲー
トf炭化膜中を流れるホットエレクトロンの一部は捕獲
中心に捕うエされ閾値屯田を変化ざぜることが知られて
いる。
First, the experimental results ζ that formed the basis of the present invention will be explained. In recent years, the high integration of MO8 devices has progressed from miniaturization (n-).On the other hand, there is a desire to be self-sufficient in the power supply voltage used.As a result, the mechanical stress applied to devices has become severe and new One of them is the hot electron effect. As a means of reducing the particle size, we use the '-beam, X, hj (
There are phosphorography and dry processes, and the high-energy particles contained in these processes damage the oxide film and harden it as hot electrons are injected. M OS F E
During the production of T, the hot electrons generated in the depletion 1 convex near the drain flow through the gate oxide film at 14 from the high i field with energy that can overcome the interface barrier of 1 (1j, for example, 5i-8iQ2). It is known that a part of the hot electrons flowing through the gate f carbide film is captured by the capture center and changes the threshold value.

そこでエツチングに伴う′・工’、 ′:F−Jrii
 3R中心の発生を調べた。第1図はエツチング試料の
構造ぽ゛i面図である。LOCO8法によりフィールド
領域(1)を形成し700へのゲート酸化11Q (2
)上のN+poly−8i(3)をレジスト(4)をマ
スクとして各催方云でエツチングする。また試料は第1
図(a)の様に博いば化膜の領域(2)がエツチング後
もすべてpoly−8i Iこ義われているものとエツ
チング後はその領域がis出する牛1図(blの21類
を用いた。エツチングの方法は通常の平行+板温の反応
性イオンエッ°チング11fi(RIE)、(1,’P
でXeC1xキシマレーザ光(308nm、4eV)を
垂直に照射する方法、フッ素ラジカルでエツチングを行
い:倶射損屓を兄生しないと考えられているケミカルド
ライエツチング法(CDE)であり、またCDEでエツ
チングした74.Arg’xキシffL/−ザ光(19
3nm、6.3eV)  を照射した試料についてもl
h’l 足G行った。
Therefore, '・Engine' associated with etching, ':F-Jrii
The occurrence of the 3R center was investigated. FIG. 1 is a structural perspective view of an etched sample. Field region (1) is formed by LOCO8 method and gate oxidation 11Q (2
) on N+poly-8i (3) is etched in each direction using resist (4) as a mask. Also, the sample is
As shown in Figure (a), even after etching, the area (2) of the film is completely poly-8i. The etching method was the usual parallel + plate temperature reactive ion etching 11fi (RIE), (1,'P
A method of perpendicular irradiation with XeC1x ximer laser light (308 nm, 4 eV), and etching with fluorine radicals: This is a chemical dry etching method (CDE) that is thought to not cause any radiation damage; 74. Arg'xxiffL/-the light (19
3nm, 6.3eV)
h'l foot G went.

以後浴試料をRIE 、XeC1、CDE 、A r 
Fと呼ぶ。
Thereafter, the bath samples were subjected to RIE, XeC1, CDE, Ar
Call it F.

測定方法6え第1図(clに示した様なエツチング後の
試料の基板f51 、 po l y−8i (31間
ζこ数十ボルトのパルス電圧を印加し基板1illから
6子を注入しくアバランシェ注入法)、注入量に対しこ
のギャパシタのフラットバンド、を圧の変化を測定する
。ごのフラットハンド(、E IEの変化量が酸化膜中
に捕えられた遣子叔に対応し、C2化膜中の電子捕獲中
心の吋を示す。
Measurement method 6: A pulse voltage of several tens of volts was applied between the substrate f51 and poly y-8i (31) of the sample substrate after etching as shown in Figure 1 (cl), and avalanche was applied to inject six particles from the substrate 1ill. Injection method), measure the change in pressure on the flat band of this gapacitor with respect to the injection amount. The electron capture center in the film is shown.

倶2図は前述の装置により測定したアバランシェ注入に
よるフラットバンド電圧VFB  のシフト漬を注入さ
れた、」荷について示している。各エツチング方法で差
は少く誤差の範囲である。
Figure 2 shows the shift dip in the flat band voltage VFB due to avalanche injection measured by the above-mentioned device for the injected load. The difference between each etching method is small and within the error range.

一方吾3r:Aは同様にmす定した薄い酸化膜の領域が
エツチング後に1j′に出する第1図(t)lのエツチ
ング後の試料の測定結果である。これを見るとXeC1
はCDEと同程度で電子捕獲中心の発生は少いと考えら
れるが、f(、IE及び八rFでははっきりと差が現わ
れ;d子(1,1!漢中心の存在が確認された。この磁
子注入を行う前に各試料について容量−電圧特性(C−
V特性)を測定すると、各エツチング方法、試料で顕著
な差は現れない。このことより礒3図で示された、几I
E 、ArFで発生した・4子;I4厩中心は4気的ζ
こ中・踵な′α電子捕獲中心一トラルトラップ)である
ことがわかる。またこのニュートラルトラップはフォー
ミングガス中での450℃30分の熱処理では減少せず
、回復させるためには800℃程度の高温の熱処理が必
要である。本災験で電子捕獲中心の発生した原因は41
図(al 、 fblの試料の比較よりR,IEのオー
バーエツチング時あるいはArFレーザ照射時に露出し
た薄い酸化膜の領域より浸入したものと考えられ、プラ
ズマ中あるいはArFレーザの高エネルギーフォトンが
薄いゲート酸化膜中で反射をくり返し形成されたことが
考えられる。
On the other hand, 3r:A is the measurement result of the sample after etching shown in FIG. 1(t)l, in which a thin oxide film region similarly etched is exposed at 1j' after etching. Looking at this, XeC1
It is thought that the occurrence of electron capture centers is similar to that of CDE, but there is a clear difference between f(, IE and 8rF; the existence of d(1,1! Han center) is confirmed. Capacitance-voltage characteristics (C-
When measuring the V characteristics, there are no significant differences between the etching methods and samples. From this, as shown in Figure 3,
E, quadruplets generated in ArF; I4 stable center is 4-ki ζ
It can be seen that this is a ``tral trap'' with the central ``α electron capture center''. Further, this neutral trap is not reduced by heat treatment at 450° C. for 30 minutes in forming gas, and high temperature heat treatment of about 800° C. is required to restore it. The cause of the occurrence of mainly electronic capture in this disaster was 41
From the comparison of the samples shown in Figures (al and fbl), it is thought that the infiltration occurred through the area of the thin oxide film exposed during R, IE overetching or ArF laser irradiation, and high-energy photons in the plasma or ArF laser penetrated into the thin gate oxide. It is thought that the particles were formed by repeated reflections within the film.

そこで次に波長200nm以下の光を透過しないフィル
ターを通してHlランプの光を照射し同様の実験を行っ
た。その結果1子捕獲中心の発生は照射損傷のないCD
E、XeCjレーザ光エツチングと同程度であることが
明らかとなった。
Therefore, a similar experiment was conducted by irradiating the light from a Hl lamp through a filter that does not transmit light with a wavelength of 200 nm or less. As a result, the development of the single-child capture center was CD without radiation damage.
It was revealed that the etching efficiency was comparable to that of E, XeCj laser light etching.

以上の実験結果に基づき本発明がなされた。以   1
下に実施例を示し説明する。第4図はM OS FET
作製の工程図である。Sl、N、膜q)をマスクとして
選択酸化法により、素子領域(9)をフィールド酸化膜
(10)で分離する( 姑41’lJ (a) fbl
 )。ここで8はフィτルドインブランテーシランによ
り形成された反転、直載である。ゲート酸化膜(11)
をブφ成女、po l y−8i (12)  を堆積
し、リン拡散により低抵抗化シた陵、レジストでエツチ
ングマスク([3)を形11文する(第4図(C))。
The present invention was made based on the above experimental results. Below 1
Examples are shown and explained below. Figure 4 shows MOS FET
It is a process chart of production. By selective oxidation using Sl, N, film q) as a mask, the element region (9) is separated by a field oxide film (10) (41'lJ (a) fbl
). Here, 8 is an inverted, direct mounting formed by a field τ field inflated silane. Gate oxide film (11)
Then, poly-8i (12) was deposited, the resistance was lowered by phosphorus diffusion, and an etching mask ([3) was formed with resist (Fig. 4(C)).

次にpoly−diをエツチングしゲート電極(14)
を形成する(渠41Aid) )。この工程まではかな
らずしも本発明で規定した2500m以上の波長光を用
いる必要はなく、高エネルギーの光を用いて各11処理
を行なえる。しかしその鳴合は照射国鵬の回りのため高
温のアニールが11必要となる。仄に不純勿を添カロし
ドレイン、ソー′ス部分(15)の接合領域を形成する
。今後のvLSIの微細化に伴いこの接合部分は極めて
浅く形成する必要があり、このあとの工程でこの不純物
分布を変化させる高説熱処理を行うことはできない。
Next, the poly-di is etched and the gate electrode (14) is formed.
(Drainage 41Aid)). Up to this step, it is not necessary to use light with a wavelength of 2,500 m or more as specified in the present invention, and each of the 11 treatments can be performed using high-energy light. However, the ringing requires 11 high-temperature annealing rounds around the irradiated Kuniho. An impurity is added slightly to form a junction region for the drain and source portions (15). With the future miniaturization of vLSIs, this junction will need to be formed extremely shallowly, and it will not be possible to perform advanced heat treatment to change the impurity distribution in subsequent steps.

そのため以後は本癒明で示した波長250nm以上の光
を用いなければならない。実際の工程ではこのn A 
l記報(16)が行なわれ、さらに保j膜としてB P
 S G (1,7)等がJ′l+、積される。またデ
バイスによっては哨2ゲートの形成、多1配線を行うた
め工程fd)〜Ig)がくり返される。そのため本厖明
の適用される工程はVLSI全工程の半分以上を占める
こととなる。
Therefore, from now on, it is necessary to use light with a wavelength of 250 nm or more as shown in this explanation. In the actual process, this n A
Recording (16) is carried out, and B P is added as a protective film.
S G (1,7) etc. are multiplied by J′l+. Further, depending on the device, steps fd) to Ig) are repeated to form two gates and conduct multiple wirings. Therefore, the processes to which this invention is applied account for more than half of all VLSI processes.

次にいくつかの個別プロセスについて説明する。Next, some individual processes will be explained.

まず第4図(elに示した床褒嘆B P S G (1
8)をエツチングする揚台を列にとる。このエツチング
は反応性ガス中にウェハを配置し、エツチングする部分
に光を集光して照射することにより各偶lこ達せられる
。しかし本発明によればここで用いられる元を少なくと
も直接ウェハに照射される光は波長200nm以上とし
て、鷹4 jJ fel (/Jゲート蛎化帷αpに1
1L子浦獲中心を作ることなくエツチングを)1ノアで
きる。また反応性ガスを活性化するために波長200n
m以下の光が必要11尚合は試料と平行に試料上方を所
定の波長の光を通」・′11させればよい。
First, the floor praise B P S G (1
8) Line up the platforms for etching. This etching is accomplished by placing the wafer in a reactive gas and focusing light onto the area to be etched. However, according to the present invention, at least the light directly irradiated onto the wafer has a wavelength of 200 nm or more,
1L can be etched without creating a 1L Koura catch center) 1 Noah. In addition, the wavelength is 200n to activate the reactive gas.
If light with a wavelength of less than m is required, light of a predetermined wavelength may be passed above the sample parallel to the sample.

一方堆積を例にとると、端4図げ)に示したlLlの配
線はAl(CH,)、(ト11メチルアルミ)雰囲気中
でArFレーザー光を照射すること(こより達成される
。しかし、波長193nmυ)A−rFレーザ−光はゲ
ート9,2化膜中に侵入すると4子捕獲中心を免生させ
ることは前述のとおりである。そこで本%ry4jこ従
いトリメ千ルサルミを分解する元(ArFレーザー元)
をウェハと半行に照射し一方選択的にノー1責を行うた
め成長200 nm以上の例えばXeClレーザー光(
308nm)をウェハ番こ果元照射して堆積を行なえば
よい。
On the other hand, taking deposition as an example, the 1L1 wiring shown in Figure 4) is achieved by irradiating ArF laser light in an Al(CH,), (T11 methylaluminum) atmosphere.However, As mentioned above, when the A-rF laser light (wavelength: 193 nm) enters the gate 9 and the dioxide film, it makes the tetrad trapping center immune. Therefore, this book%ry4j is the source of disassembling Trimesen Rusalumi (ArF laser source)
For example, XeCl laser light of 200 nm or more is used to selectively irradiate the wafer and the half-row of the wafer.
Deposition may be performed by irradiating the wafer with a wavelength of 308 nm).

このように(nullパターン形成に広く削いられてい
るプラズマプロセスに代わり、ダメージが少く7J)つ
酸化、波数堆積が1所的に低温で行え、利IXR性にす
ぐれた光プロセスが注目されている。また光照射による
異方・准エツチングも行なわれ、将来′光プロセスのV
 L S I技術への本格的適用が期待されろ現在、大
発明は多くの可能性を持つ光プロセスを無ダメージプロ
セスとして用いるために絶大な゛・力■を范揮するもの
である。
In this way, as an alternative to the plasma process, which is widely used for null pattern formation, an optical process is attracting attention because it can perform oxidation and wavenumber deposition in one place at a low temperature (7J) with less damage, and has excellent IXR efficiency. . In addition, anisotropic and quasi-etching by light irradiation is also being carried out, and in the future
Full-scale application to LSI technology is expected.At present, a great invention is exerting tremendous power to use the optical process, which has many possibilities, as a damage-free process.

また本発明の塙鍵となった第21図、第3図の夷i少、
青果よりたとえ光エネルギー元・2用いたとしてもFB
T トランジスタの活性頭載(ゲート酸化膜)まで光力
S浸入しない様にすれば照射損傷を防げること力Sわか
る。そのため嘉4図げ)でのAJM栢においても初めに
AIを適当な厚さ成長させた後はArF光を直接照射し
てもよい。このように本発明はゲート竣化膜に高エネル
ギー元を照射しないことにより多大な効果を示すもので
ある。
In addition, the 夷 i in FIGS. 21 and 3, which were the key to the present invention,
Even if you use 2 sources of light energy, FB is better than fruits and vegetables.
It can be seen that irradiation damage can be prevented by preventing the optical power S from penetrating to the active head (gate oxide film) of the transistor. Therefore, even in the AJM layer (see Figure 4), after growing AI to an appropriate thickness, ArF light may be directly irradiated. As described above, the present invention exhibits great effects by not irradiating the completed gate film with a high-energy source.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のS醍となった笑暎に哨いた仄料の断面
図、第2図及び第3図は本元明CO基賑となった火験結
果を示す特性図、弔4図は本元明の夷1A例を説明する
ための工程Vr[![i図である。 11・・・ゲート酸化膜、14・・・poly−8i、
  15・・・不純物添加領域、16・・・Aj配線パ
ターン、18・・・保護酸化膜。 代理人弁理士  則 近 憲 佑(ほか1名)嘴 第  1  図 第  1  図 ? 第4図 第  4  図
Figure 1 is a cross-sectional view of the auxiliary material used in the explosion, which is the most important feature of the present invention. The figure shows the process Vr [! [Figure i. 11... Gate oxide film, 14... poly-8i,
15... Impurity doped region, 16... Aj wiring pattern, 18... Protective oxide film. Representative Patent Attorney Kensuke Chika (and 1 other person) Beak No. 1 Figure 1? Figure 4Figure 4

Claims (5)

【特許請求の範囲】[Claims] (1)処理用のガス中に配置された試料に光照射して処
理を行う半導体装置の製造方法において、所定の光照射
処理後の工程で少なくとも前記試料に直接照射される光
を波長200nm以上としたことを特徴とする半導体装
置の製造方法。
(1) In a method for manufacturing a semiconductor device in which a sample placed in a processing gas is irradiated with light for processing, at least the light that is directly irradiated onto the sample in a step after a predetermined light irradiation treatment has a wavelength of 200 nm or more. A method for manufacturing a semiconductor device, characterized in that:
(2)前記光照射により施される処理は、エッチング、
堆積、不純物添加・拡散、酸化、であることを特徴とす
る特許請求の範囲第1項記載の半導体装置の製造方法。
(2) The treatment performed by the light irradiation includes etching,
2. The method of manufacturing a semiconductor device according to claim 1, comprising: deposition, addition/diffusion of impurities, and oxidation.
(3)前記光は試料に選択的に照射されることを特徴と
する特許請求の範囲第1項又は第2項記載の半導体装置
の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the light is selectively irradiated onto a sample.
(4)前記ガスは前記光照射により活性化されることを
特徴とする特許請求の範囲第1項記載の半導体装置の製
造方法。
(4) The method for manufacturing a semiconductor device according to claim 1, wherein the gas is activated by the light irradiation.
(5)前記試料は少なくとも半導体基板あるいは該半導
体基板上に酸化膜が形成されていることを特徴とする特
許請求の範囲第1項記載の半導体装置の製造方法。
(5) The method for manufacturing a semiconductor device according to claim 1, wherein the sample is at least a semiconductor substrate or an oxide film is formed on the semiconductor substrate.
JP59201526A 1984-09-28 1984-09-28 Manufacture of semiconductor device Pending JPS6180823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59201526A JPS6180823A (en) 1984-09-28 1984-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59201526A JPS6180823A (en) 1984-09-28 1984-09-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6180823A true JPS6180823A (en) 1986-04-24

Family

ID=16442503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59201526A Pending JPS6180823A (en) 1984-09-28 1984-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6180823A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61158136A (en) * 1984-12-29 1986-07-17 Sony Corp Vapor growth method
JPH0662401U (en) * 1993-02-12 1994-09-02 徳生 呉 Portable mini light
JP2007247335A (en) * 2006-03-17 2007-09-27 Tenox Corp Ready-made concrete pile with inside protrusion, and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5897837A (en) * 1981-12-07 1983-06-10 Fujitsu Ltd Light irradiation annealing method and device therefor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5897837A (en) * 1981-12-07 1983-06-10 Fujitsu Ltd Light irradiation annealing method and device therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61158136A (en) * 1984-12-29 1986-07-17 Sony Corp Vapor growth method
JPH0662401U (en) * 1993-02-12 1994-09-02 徳生 呉 Portable mini light
JP2007247335A (en) * 2006-03-17 2007-09-27 Tenox Corp Ready-made concrete pile with inside protrusion, and its manufacturing method

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