JPS6181029A - A/d converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an A/D converter using feedback pulse width modulation (hereinafter abbreviated as PWM).

(Prior Art) FIG. 3 is a block diagram showing an example of a conventional A/D converter using PWM. This A/D converter is
An integrator 2 that integrates the input signal Vin applied to the input terminal 1, a comparator 3 that compares the output of this integrator 2 with a reference potential (saving level), and a positive or negative polarity depending on the output of this comparator. A switch SW that applies the base Q voltage ±Es to the input side of the integrator 2, a gate circuit 5 that inputs the pulse width signal obtained from the comparator 3 and the clock signal applied to the terminal 4; The frequency divider 7 divides the frequency of the clock signal CLK and provides a square wave clock signal ±PB to the integrator 2.

Figure 4 shows the operating waveforms of the A/D converter shown in Figure 3 (
It is 4. The input signal vin is a square wave clock signal ±P
B and the voltage regulator ES, which is alternately switched by the comparator output, are applied to the integrator 2.

The integrator 2 integrates these (m) and outputs an output signal Eo as shown in FIG. 4 (l\). Konnopere-ri 3
compares the output image @EO of integrator 2 with the zero level and EO
The switch SW is driven so that +ES is negatively fed back to the integrator 2 when >O, and -ES is fed back to the integrator 2 when Eo<○. Here, the period 113 when the switch SW is in contact with the +ES side or the -ES side changes depending on the magnitude of the input signal vin, and the average value over one period is exactly the input signal Vi.
An equilibrium state is reached when n cancels out.

The square wave output signal ±PB given to the integrator 2 is applied to the integrator 2. Comparator 3. switch'!
□ Activates the PWM circuit 20 formed including SW.
” The average value for one round is zero.

Now, lower the opening gate where the switch SW is touching the +ES side.
, - If the open gate in contact with ES 11111 is T2, then in the equilibrium state, the input resistance R1 and the resistance Rf are Ri =
If R1°, the following equation holds true.

Vin・Ding−ES (T2−T1) Vin/EEs = (T2−Tl)/T In this equation, T=T++72 is the period of the square wave clock, and the input signal Vin is the pulse width of the reference voltage ES. The counter 6 counts the clocks output from the gate circuit 5, so that
The difference in pulse width (T2 Tl) is equal to 1, and the input signal ■in is thereby digitized.

(Problem to be Solved by the Invention) In conventional A/D converters that operate in this manner, the accuracy of A/D conversion depends on the integration constant, square wave clock voltage, and integrator 2.
The A/D conversion time is regulated by the period of the square wave clock, and the A/D conversion time is regulated by the period of the square wave clock. There is a problem in that when the A/D conversion time is shortened, the resolution is correspondingly reduced.

The present invention was made in view of the above-mentioned problems in the prior art (1) and (6), and its purpose is to develop an A10 system that can perform high-resolution AlO2 exchange in a short time by adding a simple circuit. The goal is to demonstrate the power of conversion.

(Means for Solving the Problems) The present invention for solving these problems includes a first integrator to which an input signal, a square wave clock, and a positive/negative polarity standard signal are input; A pulse that includes a first comparator that compares the output of the integrator with a zero level, and a switch that alternately switches the i'IE negative polarity base ill signal according to the output of the first comparator. In an A/D converter using the i!-type pulse width modulation method, which uses a width modulation circuit and a pulse width (m) obtained from this pulse width modulation circuit to obtain a digital signal, the input signal is and positive depending on the pulse width signal from the pulse width modulation circuit.

a second integrator to which a reference signal that switches from negative to negative is applied; and a second integrator that compares the output of this second integrator with the level.
a comparator, and a predetermined weighting according to the output of the second comparator/; means for negatively feeding the signal to the second integrator;
The device is characterized in that it is provided with means for determining the number of hours the tIl electric current is open.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In this figure, parts corresponding to those in FIG. 3 are given the same reference numerals, and their explanations will be omitted. The A/D converter of the present invention is the one shown in FIG. 3, in which the input signal vin is input through the switch SW○, and the feedback type
The reference signal ± of positive and negative polarity switches in accordance with the pulse width of the pulse width signal outputted from the comparator 3 to 4q of the circuit 20.
ls as "an input integrator 8, a comparator 9 that compares the output of this integrator 8 with the zero level, and a signal (-Es/100) with a predetermined weight pt subtracted according to the output of this comparator 9. A feedback means 10 for feeding n feedback to the input side of the integrator 8 and means (a gate circuit 11 and a second counter 12) for counting the discharge time of a predetermined weighted signal are installed.

FIG. 2 is an operational waveform diagram showing waveforms at each point of the device shown in FIG. The pulse width signal PN outputted from the comparator 3 is outputted from the flip-flop circuit FFI, respectively.
is applied to FF2, where clock signals CL and K are used to control the period of this clock signal CLK. Converts into a dandelion. The output of the flip-flop FF2 is further passed through the flip-flop FF3 to 1 of the clock signal CLK.
The state of the "H" level is made to be better than the original state for a period of time.

These suspended pulse width signals are sent to the gate circuit Gl.
, G2. Pulse width signals PH and PL via G3,
With this pulse width ( ), switch SW 1 is set to -
ES (It! I and +ES side are alternately driven, and 1 s of reference current output of positive and negative polarity is applied to the input terminal of the integrator 8 during one period of the pulse width signal. At the same time, the switch SWO is turned on the gate It is driven by the signal PG passed through the circuit G4, and provides an input current 1 in 2 corresponding to the input signal g and V in for one period (T) of the pulse width signal.Thereby, the integrator 8 performs subtraction between the input signal 1in2 and a signal corresponding to the difference in pulse width of the pulse width signals during one period of the pulse width signal.Then, at the end of one period of the pulse width signal, the input signal 1in2 is subtracted from the input signal 1in2. [The difference between the inflow current due to in2 and the suspended time length inflow or quasi current ±Is (hereinafter referred to as protonization II The voltage remains as ■ε.

Next, during two periods of the pulse width signal, this surplus voltage Vε
switch S through gate circuit G5 so that
Driving W2, a signal (-E s / 100 in this example) subjected to a predetermined weighting IJ is sent to I through the resistor 17r.
A reference current of f=-Is/100 is negatively fed back to the input side of the integrator 8 and discharged.

The discharge time (time until the surplus voltage Vε becomes zero) T2 based on the reference current=Is/100 is measured by the gate circuit 11 and the second counter 12 to which the pulse width signal from the comparator 9 is input.

Through such an operation, the input lightning current in the digits that cannot be measured as a count value by the first counter 6 is reduced to -Is/10.
By changing the blue color with a reference current of 0, it is multiplied by 100 and becomes 31, which is -C.

Now, the muntinization error current is expressed as Δ(in, clock signal CLK
Letting the period of Δt be Δt, these have a relationship as shown in equation (1).

−Is ・Δt〈△Jin−100−Δt<ls−Δt
(1) Also, since :1 at the second counter 12, 1 direct N2 is (2
) is expressed by the formula.

(fs/100-Δl1n) ・100-Δt=N2.
Δt-1s/100 (2) (1> formula, (2
) formula, the count value N2 is 0<N2<200
Take the range of (3).

As is clear from the operation waveform diagram not shown in FIG. 2, in one period (3t) of the signal PG that drives the switch SWO,
The sum of the charges stored in the capacitor of the integrator 8 becomes zero.If one sign shown in Fig. 2 is used as is, (4)
Equation 17 is given.

1s(-r++Δt)-(Is('r-T+ ＞+
[1n-T) = ls-T2/100
(4) In equation (4), T+=N+ ・Δt (
Nl is the first karan'I 6 (1) jt number hfi)
, T==100·Δt.

When Tz=Nz·Δt, equation (5) is obtained.

ls(N,+1)Δt−Is(+00−N[)Δt
+ 1001 in-Δ to -IS -N2 ・Δt7/1oo (5
) When formula (5) is transformed, formula (6) becomes 1! t be beaten.

1 in= (TS / 10000) (100(
2N+ -ion>+ (100-N2) J
(6) Similarly expressed for the case of the conventional example shown in FIG. 3, the equation (7) is obtained.

11n-(is / 10000) ・100・(2N
+ -100) In formula (6), 1ilHJ of N2:
From formula (3), 0~20017)Iil'i wo(!:
le/j me, (+00-NZ) (DIJMha, l (100-NZ) l < 100
(8) becomes.

As is clear from the comparison of equations (6) and (7), in the case of the device of the present invention (formula (6)), equation (7) (conventional example) has a ratio of 2N, -100: 100 It can be seen that the resolution is improved by two orders of magnitude throughout [in].

In order to achieve similar resolution with conventional equipment,
The frequency division ratio of the clock signal CLK must be increased from 100 to 10,000, and in this case, the conversion time becomes 100 times greater.

In the device of the present invention, the time required for Δ/D conversion is
Since it requires three times the period T of the pulse width signal, it ends up being the conventional one! In order to achieve the same resolution as the original position, the Δ/D conversion time will be 3/100, which can be reduced to approximately 1/33.

(Effect of Light) As explained above, according to the present invention, the integrator 8, the comparator 9. By adding a simple circuit consisting of the second counter 12 and the like, an A/D converter that can perform high-resolution A/D conversion in a short time can be realized.

[Brief explanation of drawings]

FIG. 1 is a pocket block diagram of an example of the device according to the present invention, FIG. 2 is an operational waveform diagram thereof, FIG. 3 is a block diagram of a conventional device, and FIG. 4 is an operational waveform diagram thereof. 1...Input terminal 2.8...Integrator 3.9...
Comparator 5.11...Gate circuit 6.12...Counter 10...Feedback means SW, SWO, SWl, SW2. ... Switch patent applicant Representative of Yokogawa Hokushin Densho Co., Ltd. Patent attorney Makoto Ozawa

Claims (1)

[Claims] a first integrator that receives an input signal, a square wave clock, and a reference signal of positive and negative polarity; a first comparator that compares the output of the first integrator with a zero level; A pulse width modulation circuit comprising a switch that alternately switches the positive and negative polarity reference signals according to the output, and a circuit for obtaining a digital signal using the pulse width signal obtained from the pulse width modulation circuit. In a feedback pulse width modulation type A/D converter, the input signal is applied via a switch, and a reference signal whose polarity is switched between positive and negative depending on the pulse width signal from the pulse width modulation circuit is applied. a second integrator that compares the output of the second integrator with a zero level; and a second comparator that compares the output of the second integrator with a zero level; An A/D converter comprising: means for providing negative feedback to the integrator; and means for counting the discharge time of the predetermined weighted signal.