JPS6183339U - - Google Patents
Info
- Publication number
- JPS6183339U JPS6183339U JP1984167613U JP16761384U JPS6183339U JP S6183339 U JPS6183339 U JP S6183339U JP 1984167613 U JP1984167613 U JP 1984167613U JP 16761384 U JP16761384 U JP 16761384U JP S6183339 U JPS6183339 U JP S6183339U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- time constant
- comparison
- constant circuit
- inverting input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
第１図各点の信号波形を示す図、第３図は他の実
施例を示す図、第４図は遅延パルス発生を説明す
るのに供する図、第５図ａは従来例を示すブロツ
ク図、同図ｂは具体的回路例を示す図である。
１１…時定数回路、１２…放電用トランジスタ
、１３，１４…比較回路、１５…論理回路。
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing signal waveforms at each point in Fig. 1, Fig. 3 is a diagram showing another embodiment, and Fig. 4 is a diagram showing delayed pulse generation. FIG. 5A is a block diagram showing a conventional example, and FIG. 5B is a diagram showing a specific circuit example. DESCRIPTION OF SYMBOLS 11... Time constant circuit, 12... Discharge transistor, 13, 14... Comparison circuit, 15... Logic circuit.
Claims (1)
の時定数回路を構成するコンデンサと並列に接続
された放電用素子と、前記時定数回路の出力端に
非反転入力端子が接続された第１比較回路と、前
記時定数回路の出力端に反転入力端子が接続され
た第２比較回路と、前記第１及び第２比較回路か
らの出力の論理積をとる論理回路とを備え、該論
理回路より遅延出力を得るようにしたことを特徴
とする遅延回路。 a time constant circuit arranged between a power supply and ground; a discharging element connected in parallel with a capacitor constituting the time constant circuit; and a first non-inverting input terminal connected to the output end of the time constant circuit. a comparison circuit, a second comparison circuit in which an inverting input terminal is connected to an output terminal of the time constant circuit, and a logic circuit that takes an AND of outputs from the first and second comparison circuits, the logic circuit A delay circuit characterized in that it obtains a delayed output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984167613U JPS6183339U (en) | 1984-11-05 | 1984-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984167613U JPS6183339U (en) | 1984-11-05 | 1984-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183339U true JPS6183339U (en) | 1986-06-02 |
Family
ID=30725402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984167613U Pending JPS6183339U (en) | 1984-11-05 | 1984-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183339U (en) |
-
1984
- 1984-11-05 JP JP1984167613U patent/JPS6183339U/ja active Pending
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