JPS618371U - integral circuit - Google Patents
integral circuitInfo
- Publication number
- JPS618371U JPS618371U JP9171884U JP9171884U JPS618371U JP S618371 U JPS618371 U JP S618371U JP 9171884 U JP9171884 U JP 9171884U JP 9171884 U JP9171884 U JP 9171884U JP S618371 U JPS618371 U JP S618371U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- waveform
- emitter
- load
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の積分回路を示す回路図：第２図及び第
３図は本考案の積分回路に被積分波形を入力した時の各
部の波形を示す波形図である。
主な図番の説明、２・・・電源ライン、３・・・抵抗、
６ａ＋ ６ｂｔ ６ｃｔ ６ｄ＊ ６ｅ，６ｆ
””｝ランジスタ、ａ＊ ７ｂｔ ７ｃｔ ７ａ
，７ｅ，７ｆ−ｃミツタ接地型トランジスタ、８ａ，８
ｂ，８ｃ，８ｄ，８ｅ，８ｆ・・・負荷抵抗、■・・・
シフトレジスタ、１１・・・データ入力端子、１２・・
・−クロツク入力端子。FIG. 1 is a circuit diagram showing an integrating circuit of the present invention; FIGS. 2 and 3 are waveform diagrams showing waveforms at various parts when a waveform to be integrated is input to the integrating circuit of the present invention. Explanation of main drawing numbers, 2...power line, 3...resistance,
6a+ 6bt 6ct 6d* 6e, 6f
””}Ran resistor, a* 7bt 7ct 7a
, 7e, 7f-c Mitsuta grounded transistor, 8a, 8
b, 8c, 8d, 8e, 8f...Load resistance, ■...
Shift register, 11...Data input terminal, 12...
-Clock input terminal.
Claims (1)
接続すると共に各々のベース電位が所定電位に保持され
るｍ個のトランジスタ（ｍは整数）と、負荷抵抗を介し
て各々のコレクタを前記ｍ個のトランジスタの各々のエ
ミツタと接続したｍ個のエミツタ接地型トランジスタと
、ｍ個のフリツプフロツプから構成されて該ｍ個のフリ
ツプフロツプの各々のビット出力端子を前記ｍ個のエミ
ツタ接地型トランジスタの各々のベースと接続したシフ
トレジスタとより成り、該シブトレジスタのデータ入力
端子に被積分波形を、かつクロツク入力端子に前記被積
分波形のセ音周期（ｎ≧ｎ ｍ，−ｎは整数）のクロツクパルスを入力し、前記ｍ個
のトランジスタが順次オンすることによって加算された
コレクタ電流及び前記負荷による電圧降下より積分波形
を得ることを特徴とする積分回路。[Claims for Utility Model Registration] m transistors (m is an integer) each having a common collector, connected to a power supply line via a load, and each having a base potential maintained at a predetermined potential, and a load resistor. m common emitter transistors each having a collector connected to the emitter of each of the m transistors through the m flip-flops, and a bit output terminal of each of the m flip-flops connected to the m transistors. It consists of a shift register connected to the bases of each of the emitter-grounded transistors, and the data input terminal of the shift register is connected to the waveform to be integrated, and the clock input terminal is connected to the waveform to be integrated. - n is an integer), and an integral waveform is obtained from the collector current added by sequentially turning on the m transistors and the voltage drop due to the load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9171884U JPS618371U (en) | 1984-06-19 | 1984-06-19 | integral circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9171884U JPS618371U (en) | 1984-06-19 | 1984-06-19 | integral circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS618371U true JPS618371U (en) | 1986-01-18 |
| JPH044285Y2 JPH044285Y2 (en) | 1992-02-07 |
Family
ID=30647856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9171884U Granted JPS618371U (en) | 1984-06-19 | 1984-06-19 | integral circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618371U (en) |
-
1984
- 1984-06-19 JP JP9171884U patent/JPS618371U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH044285Y2 (en) | 1992-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS618371U (en) | integral circuit | |
| JPS60124045U (en) | Output transistor protection circuit | |
| JPS582018U (en) | power circuit | |
| JPS591236U (en) | High voltage pulse generation circuit | |
| JPS599638U (en) | Simple D/A converter | |
| JPS58141630U (en) | Multivibrator circuit | |
| JPS59162720U (en) | switch input circuit | |
| JPS5850505U (en) | Muting drive circuit | |
| JPS592162U (en) | Hall effect semiconductor integrated circuit | |
| JPS59128573U (en) | Overcurrent detection circuit | |
| JPH01159426U (en) | ||
| JPS60155278U (en) | Adder circuit | |
| JPS60134320U (en) | Amplifier circuit coupled to differential amplifier circuit | |
| JPS5969521U (en) | voltage generation circuit | |
| JPS5857109U (en) | Charge transfer device drive circuit | |
| JPS59140514U (en) | amplifier circuit | |
| JPH03237809A (en) | Amplifier circuit | |
| JPS6069595U (en) | Bipolar drive circuit protection device | |
| JPS58166123U (en) | limiter circuit | |
| JPS60174919U (en) | Reference voltage generation circuit | |
| JPS6030635U (en) | flip flop circuit | |
| JPS59147230U (en) | reset circuit | |
| JPS61264910A (en) | Level shift circuit | |
| JPS611930U (en) | ECL circuit | |
| JPS6126350U (en) | stereo indicator circuit |