JPS6184847A - Gate array master slice ic device - Google Patents

Abstract

PURPOSE:To improve the characteristic of signal transmission speed, etc. and increase the integration degree while keeping the wiring redundancy of wiring channel regions by mixing one-column type basic cell arrays capable of unit cell wiring on any side and two-column type basic cell arrays restricted in unit cell wiring. CONSTITUTION:A two-column type basic cell array BC2 is provided between one-column type basic cell arrays BC1. A wiring channel region CH is provided on the outside of the two-column type basic cell array BC2, but no wiring channel region exists between each of one-column type basic cell arrays BC1-1 and BC1-2 in that array BC2; besides, these arrays BC1-1 and BC1-2 are arranged in right-left symmetry. Therefore, the restriction in use of wiring channel regions of the arrays BC2 can be sufficiently compensated because the arrays BC1 can select any of wiring channel regions.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a quad array master slice integrated circuit device.

Generally, large scale integrated circuits (such as complex integrated logic circuits)
Logic LSIs (hereinafter referred to as "logic LSIs") are produced in small quantities in a wide variety of products in order to be manufactured according to customer requirements.

A master slicing method has been proposed as a method for manufacturing such high-mix, low-volume logic LSIs quickly and at low cost.

The mask slicing method involves manufacturing a large number of basic cells regularly in advance, manufacturing wiring/mother-turn masks for unit cells according to customer requirements or developed products, and cutting the wiring and wiring within these basic cells. Only the wiring between basic cells is manufactured separately later. Therefore, the manufacturing or development period is shortened, and the basic cell structure is
Since it is common to I, manufacturing or development costs are also reduced.

Note that the basic cell structure is determined by the impurity diffusion region in the semiconductor substrate and the minimum necessary wiring in the basic cell, so it is also called the bulk structure.

The present invention improves the bulk structure of the f-) array master slice logic LSI in which the basic cells described above are arranged in an array.

Prior Art FIG. 2 shows an equivalent circuit showing an example of a basic cell used in a complementary MIS (αIS) quadrature array, FIG. 3 is a plan view thereof, and FIGS. A sectional view taken along the IV-IV line and a sectional view taken along the v-v5 line are shown, respectively.

As shown in Figure 2, this basic cell consists of a pair of P-channel transistors Q, , , Q,2 that share a source (or drain) and a pair of N-channel transistors that share a source (or drain). Qn+'Q
n2), these transistor pairs of different conductivity types Q, 1. This is due to the fact that Qn4, Qp2 and Qn2 are commonly connected. Please refer to Figure 3 ~ Figure χ5!
To explain the manufacturing method of B, the above-mentioned basic cell has an N-channel transistor Qn4. A P-well 2 is formed as a Qn2 formation region, and then a field oxide film 3 is formed as an isolation layer. Next, a date oxide film 4 for each transistor is formed, and a P channel transistor Q is further formed in the N-silicon substrate 1.
, 4 + Q, 2, a P impurity diffusion layer 5 for the N-channel transistor is formed in the P-well, and finally, a P impurity diffusion layer 5 for each transistor QP'' is formed in the P-well.
' Dart of Qnl and each transistor Q, 2 *
A polysilicon layer 7 in which the gates of Qn2 are commonly connected is formed to complete the pre-process for forming the bulk structure. The subsequent steps are performed using unit cell masks according to customer requirements or developed product types.

Conventional basic cells are arranged in a play shape in the center of a chip, as shown in FIG. Toe 9, each array BC
I consists of one column of basic cells, and a wiring channel region CH is provided between them. In FIG. 6, Ilo is an input/output circuit for external connection, and P is a pad.

FIG. 7 shows an example in which unit cells are configured in the above-mentioned one-column basic cell array BCI. The wiring LA shown by the solid line parallel to the basic cell array BCI is formed of the first aluminum layer, and is perpendicular to the basic cell array BC. The wiring LB shown by the dotted line is formed from the second aluminum layer. Such wiring LA and LB provide wiring between unit cells and unit cells.

Problems to be Solved by the Invention However, when unit cells are configured in the above-mentioned one-column basic cell array BCI, the vertical length of one unit cell becomes too long.Therefore, the above-mentioned wirings LA and LB also become long, and the signal transmission speed is reduced. Inviting characteristics such as! i, wiring LA, LB
As a result, the wiring channel region CH between the basic cell arrays has to be enlarged, which is disadvantageous in terms of the degree of integration.

In order to solve the above-mentioned problem, one idea is to configure the basic cell array with two rows of basic cells. Therefore, the above-mentioned wirings LA and LB can be shortened to improve characteristics such as signal transmission speed, and the wiring channel area between basic cell arrays can also be made smaller to improve the degree of integration.

However, as shown in FIG. 8, if all the basic cell arrays are simply configured with such two-row basic cell arrays, in the two-row basic cell array, the wiring for unit cells will only be on one side. For this reason, a two-column basic cell array such as BC2
-2, for example, there is no wiring allowance in the wiring channel area CH, and even if there is wiring allowance in the wiring channel area CH on the opposite side, it is impossible to wire the unit cells of the two-column basic cell array BC2-2. As a result,
Unwiring occurs.

Means for Solving the Problems The purpose of the present invention is to address the above-mentioned problems of the conventional method, and to solve the problems of the conventional type described above. By mixing column-type basic cell arrays, it is possible to improve characteristics such as signal transmission speed while maintaining wiring redundancy in the wiring channel area, and also reduce the wiring channel area between basic cell arrays to increase the degree of integration. The purpose is to improve.

Embodiment FIG. 1 is a plan view showing an embodiment of an f-) array master slice integrated circuit device according to the present invention.

In FIG. 1, a two-column basic cell array BC2 shown in FIG. 9 is provided between the one-column basic cell array BCI. As shown in FIG. 9, a wiring channel region CH is provided outside the two-column basic cell array BC2.
There is no wiring channel region between each one-column basic cell array BCI-1, BCI-2 in the one-column basic cell array BCZ.
I-2 are arranged symmetrically.

FIG. 10 is a plan view showing an example of wiring for unit cells in the two-row basic cell array shown in FIG.
FIG. 1 is a plan view of the single-column basic cell array BCI shown in FIG. 1 with wiring for the same unit cells. As can be seen by comparing Figures 10 and 11, in Figure 10,
The number of basic cell stages used is 4, whereas in FIG.
The wiring (shown by a dotted line and its contact shown by a single circle) is generally shorter in FIG. 10 than in FIG. 11. Further, the intervals between the wirings LB1 to LB5 of the second layer aluminum (shown by dotted lines and their contacts shown by double lights) for connection with other unit cells are also short. As a result, the wiring channel region CH for connection with other unit cells
The number of wires passing through can be reduced, and the length of the wires can also be shortened.

In FIG. 10, unit cell wiring LB1 to LB,
Among them, LBl and LB2 #LBs are located only on one side of the basic cell array BC2, whereas LB
4. LBs are located on both sides.

Finally, 9, LB, %LB, must be connected to the wiring in the wiring channel region on one side. On the other hand, in FIG. 11, the unit cell wirings LB1 to LB are all located on both sides of the basic cell array BC'l, which means that the wiring channel regions on either side can be used.

In the present invention, a single-column basic cell array BCI is arranged in parallel and opposed to at least one side of the two-column basic cell array BC2. Therefore, the two-column basic cell array BC
The restriction on the use of the wiring channel area of No. 2 can be sufficiently covered by the single-column basic single-array BCI because any wiring channel area can be selected. -4I) If the unit cell wiring for the two-column basic cell array BC2 is determined before the unit cell wiring for the one-column basic cell array BCI, the possibility of unwired wiring is reduced.

In addition, in the above-mentioned embodiment, the 1-row type, 2-row type, and 1-row type are arranged repeatedly, but this can also be done in other forms as long as the 1-row type and the 2-row type are adjacent to each other. obtain. For example, 1
It may be a repeating row type or two row type. In addition, although 1 used a basic cell consisting of two P-channel transistors and the same number of N-channel transistors, with the gates of six pairs of P-channel/N-channel transistors connected in common, 3 and more It is also possible to use a configuration consisting of a plurality of P-channel transistors and the same number of N-channel transistors, or a configuration in which six pairs of P-channel/N-channel transistors are commonly connected.

As described in detail, according to the present invention, since the one-column basic cell array and the two-column basic cell array are mixed, the wiring channel is reduced due to the reduction in the wiring length and the number of wirings in the two-column basic cell array. In addition to improving the collection accuracy, it is also possible to prevent unwired lines due to restrictions on the used distribution channel area of the two-row basic cell array.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of a card array master slice integrated circuit device according to the present invention, and FIG.
An equivalent circuit showing an example of a basic cell used in an ISf-door array, FIG. 3 is a plan view of FIG. 2, and FIGS. 4 and 5 are cross-sectional views taken along lines IV-■ and ■-■ in FIG. 3, respectively. 6 is a plan view of a conventional date array master slice integrated circuit device U, FIG. 7 is a diagram showing unit cell wiring in the one-row type basic cell array shown in FIG. 6, and FIG. 8 is a two-row type basic cell array shown in FIG. Diagram showing wiring for unit cells in a type basic cell array, No. 9
The figure is an enlarged plan view of the two-row basic cell array in Figure 1.
Figure 0 is a diagram showing an example of wiring for uni and tocells in the two-row basic cell array BO2 in Figure 1, and Figure 11 is a diagram showing 1 in Figure 1.
10 is a diagram in which a column-type basic cell array BCI is provided with the same wiring as the unit cell in FIG. 10. FIG. BCI: 1-column basic cell array, BO2: 2-column basic cell array, CH: wiring channel region.

Claims (1)

[Claims] 1. A plurality of first basic cells in which at least one pair of P-channel MIS transistors and an N-channel MIS transistor are arranged in parallel, and a plurality of second basic cells in which the arrangement of transistors is a mirror image of the first basic cell. a two-row type basic cell column in which the first basic cell column and the second basic cell column are arranged closely; and the first or second basic cell column. 1. A gate array master slice integrated circuit device, characterized in that gate array master slice integrated circuit devices are arranged to sandwich a wiring area.