JPS6184952U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an arithmetic device according to the present invention, and FIG. 2 is a diagram for explaining a conventional arithmetic device. In the figure, 1 is the central processing unit, 2 is the input/output bus, 3 is the microprogram control circuit, 4 is the microprogram memory, 5 is the microprogram register, 6 is the function operation memory section, 7 is the input/output control circuit, and 8 is the argument 9 is a function selector, and 10 is a function memory. In the drawings, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] In the arithmetic unit of a digital computer, in order to perform functional operations, there is an input/output control circuit that takes in the function data sent from the central processing unit through the input/output bus and sends out the function value, and a function that stores the function value. In order to read the function value corresponding to the function data from the function memory, if the function data is taken into the input/output control circuit, select which function is to be calculated, and write the function value to the address of the function memory. An arithmetic device comprising a function operation memory unit comprising a function selector that converts and outputs, and an argument register that takes in arguments of the function data, converts them to addresses of the function memory, and outputs them.