JPS6187300A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the generation of unbalance of a capacity between bit line and to generate a precise reference level easily, when the signal read from the memory cell is amplified by specifying a circuit of a dummy cell. CONSTITUTION:A dummy cell DC and two dummy capacities CR1 and CR2 are pre-charged through a bit line B1, and through either of these two dummy capacities, a precharging level in the dummy cell DC is changed by a capacity coupling and on the bit line B1, a reference level to amplify the optimum fine signal can be easily made. A capacity unbalance of a bit line forming a pair can be completely eliminated, and the effect that an action margin of the sense amplifier become larger can be obtained. Further, two lines of the dummy word line DW and the level shift signal line Z are sufficient, and one line can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dummy cell of a semiconductor memory, particularly a dynamic memory. For convenience, the following explanation will be based on an example using an N-channel MO8FET, but the present invention can also be applied to a P-channel MO8FET.
Any other insulated gate transistor is essentially equally applicable.

(Prior art and its problems) Typical circuits of conventional dynamic memory include, for example, Nikkei Electronics (January 8, 1979 issue, 1
10 to 133).

FIG. 3 shows the configuration around the bit line and sense amplifier of a conventional dynamic memory. In the figure, 8A is a sense amplifier, BO and Bl are bit lines, MC is a memory cell, and D
C' is a dummy cell, W is a word line, DW is a dummy word line, PR is a reset signal line, SE is a sense amplifier activation signal line, P is a bit line precharge signal line, and CB, C8, and CR are respectively Shows bit line capacitance, cell capacitance, and dummy capacitance.

The operation of this dynamic memory will be explained. First, set the signal lines P and PR to high level to connect MOSFET To
.

TI and T4 are turned on, the bit lines BO and Bl are precharged to the potential ■, and the dummy capacitor CR is precharged to the potential VR.

Next, set the signal lines P and PR to low level to connect the MOSFET.
To.

'ri, T4 is turned off, and the bit lines BO and Bl are placed in a floating state. Here, set the word line W to high level and M
Binary information, that is, the charge stored in the cell capacitor C8, is read out from the memory cell MC to the bit line BO through the OSFET T2, and the dummy word line flow is also read out.

A constant reference level is generated on the bit line B1 through MOSFET T3 by setting it to a high level at times. Then, the slight /T signal read out between the bit lines BO and B1 is set to a high level on the sense amplifier activation signal line SE. This activates the sense amplifier and amplifies it.

The level of 7 Allen level generated on the bit line B1 at this time is determined by changing the levels of the dummy capacitors CR and VR so that the level is between the two levels of the bit line BO that occur when binary information is read from the memory cell MC. able to make.

Usually, VR=GND "1' CR=O8/2, or VR=VD/2 and CR=C8.

Here, ■ is the highest voltage stored in the cell capacitor CS, which is usually equal to the power supply voltage used. If CR=O8/2, the capacitance attached to the bit line pair when the sense amplifier is activated becomes an irregular value (CB + C8) CB + CR), resulting in a drawback that the operating margin of the sense amplifier becomes narrow. If -171cCR=C8, there will be no irregularity in the capacitance on the bit line, but it will be accurate as vR.
The drawback was that it was extremely difficult to make a /2.

(Object of the Invention) An object of the present invention is to provide a dummy cell that does not cause capacitance imbalance between bit lines when amplifying a signal read from a memory cell, and that easily generates an accurate 7 Allen level. Our goal is to provide semiconductor memory with

(Structure of the Invention) The present invention includes at least one pair of bit lines, a plurality of memory cells connected to the bit lines and storing binary information,
a pair of dummy cells connected to the bit line pair for generating a constant reference level on the bit line; and a ninth word line for controlling signal transfer between the bit line and the memory cell; The dummy cell includes a dummy word line for activating the dummy cell, and a sense amplifier provided for each bit line pair for amplifying a minute signal read out from the memory cell and the dummy cell. Consisting of one MISFET and first and second dummy capacitors, the drain, r-to, and source of the MISFET are connected to the bit line, the dummy word line, and the first dummy capacitor, and the The semiconductor memory is characterized in that the second dummy capacitor is connected between the source and the level shift signal line.

(Examples) The present invention will be described in detail below using typical examples to aid understanding.

FIG. 1 is a circuit diagram of a dummy cell showing an embodiment of the present invention, which is used in place of the conventional dummy cell DC' shown in FIG. Also, the same symbols are used for parts equivalent to those in Fig. 3. 2 is a level shift signal line for controlling the precharge level of the nodes in the dummy cell. Figure 2 is an operational waveform diagram of the embodiment shown in Figure 1. .1 The voltage waveforms at each part when information is read are shown by broken lines and solid lines.

The operation when the dummy cell DC of FIG. 1 is placed in place of the dummy cell DC' of FIG. 3 will be described with reference to FIG.

Keep the bit line recharge signal @p, dummy word line source and level shift signal line 2 at high level, and bit line BO#
Bl and the node R in the dummy cell C are precharged to level vP. And dummy word line y? If, set to low level, MO8F]li:T Turns off T3 and disconnects node R from the bit line. Next, level shift signal line 2
to a low level. At this time, the level VRI of the node R is lowered by the force of the dummy capacitor CR2, f ring, and becomes as follows. Here, the level amplitude of the level shift signal line z by vz is shown. After that, the precharge signal line P is set to a low level, so that the bit lines BO and BL are in a floating state at the level vP, and the word line W and the dummy word line DW are set to a high level, so that binary information is transferred from the memory cell MC to the bit line BO. At the same time as reading, a reference level for amplifying this minute signal in the sense amplifier 7' SA is generated on the υ bit line l by the dummy cell DC, and then the sense amplifier S
After activating A and amplifying the minute signals on the pit lines BO and Bl and completing a series of R output operations, the word line W is set to a low level to disconnect memory cell 51C from the bit line BO and the sense amplifier SA is activated. Inactive. In the conventional memory, the dummy word line (2) is brought to a low level at approximately the same time as the word line W, but in the present invention, it remains at a high level even when the word line W goes to a low level. And precharge signal line P
to high level and bit lines BO and Bl to level VPK''
Precharging is performed, but at the same time, the level shift signal line 2 is set to high level so that the node R is also at the level VP K MO
Precharge bit line B1 through SFET T3. The level of the dummy word line TS at the time of precharging needs to be at least such a level that the pit line BL and the node R are electrically connected to Z>E to turn on the MO8FET T3.

The above is the operation of the memory of the present invention. In the present invention,
Let the precharge level of pit lines BO and Bl be vp, the O information level of memory cell MC be CND (OV), and the 1 information level be VD, and the bit line BO when O information and 1 information are read from memory cell MC. Each level is V
BO and VBI, Bi,) mBl Nori 7 Allen level is expressed in VBR. Here "t' CRI +CR2= C8, VR
When I = VD/2, the above equation yields the following result: VBI - VBR = VBR - VBO. That is, when the sense amplifier amplifies a minute signal corresponding to 0 or 1 information read from the memory cell/14c, the dummy cell PC according to the present invention
CRI +CR2= C8,! -VRI
It can be seen that the reference level VBR when satisfying the condition of =VD/2 is the optimal level. For example, if we set vp = vz = VD in the formula mentioned earlier, then these conditions! 0 A solution of CR1=CR2=C8/2 is obtained. Also, it is clear that the optimal solution can be obtained even when vp ) vz
Then, CBO= CB + C3 CBI = CB + CRI + CR2,
Since CR1+CR2=C8, CBO=CB
There is no capacitance imbalance in this pair of pit lines. Therefore, the operating margin of the sense amplifier is increased, and even a read signal from a smaller memory cell can be amplified accurately compared to the conventional one.

In the above explanation, the case where the level change of the dummy word line and level shift signal line from high level to low level is performed immediately before the precharge signal line becomes low level, but these level changes are After the charge signal line goes high and the internal node of the dummy cell DC is recharged to level vpic7'' via the bit line, it is allowed until just before the word line goes high. (not shown in Figure 3) may remain at a low level as in the past, but while the precharge signal line is at a high level, the level in the dummy cell DC is set to the same level as the selected dummy word line. The level can also be refreshed.Furthermore, the time when the level shift signal line and unselected dummy word line are set to high level does not need to match the time when the grid charge signal line is set to high level.
The sense amplifier makes the small signal on the pit line moderately large.
A (There is no problem as long as it is after the time when the signal is amplified and becomes large enough to be unaffected by the noise generated due to the level change of these signal lines.

(Effects of the Invention) As detailed above, in the semiconductor memory of the present invention, the two dummy capacitors in the dummy cell are precharged to the same level as the bit line via the pin IN, and the two dummy capacitors are precharged to the same level as the bit line. By changing the precharge level in the dummy cell through capacitive coupling through one of the two, it is possible to easily create a reference level for optimal microsignal amplification on the bit line, and the capacitance of the paired bit line. The effect is that there is no unbalance at all, and the operating margin of the sense amplifier is increased.

Furthermore, in order to drive a dummy cell in a conventional semiconductor memory, three wires, a dummy word line, a reset signal line, and a VR power supply line, are required, but in the present invention, a dummy word line and a level shift signal line are required. With just two, the number of arrangement can be reduced by 11.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a dummy cell showing an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the embodiment shown in FIG. 1, and FIG.
The figure is a diagram showing the configuration around bit lines and sense amplifiers of a conventional dynamic memory. In the figure, SA is a sense amplifier, BO, BI hub, T line pair, MC is a memory cell, DC is a dummy cell, W is a word line, DW is a dummy word line, 2 is a level shift signal line, CB is a bit line capacitance, C8 is cell capacity, CR1, CR
2 indicates a dummy capacitance. Figure 1 Figure 3

Claims (1)

[Claims] (1) at least one pair of bit lines, a plurality of memory cells connected to the bit lines for storing binary information, and a plurality of memory cells connected to the bit line pair for generating a constant reference level on the bit lines; a pair of dummy cells, a word line for controlling signal transfer between the bit line and the memory cell, a dummy word line for activating the dummy cell, and the memory cell and the dummy cell. a sense amplifier provided on each bit line pair for amplifying read minute signals; the dummy cell includes one MISFET and first and second dummy capacitors; the drain of the MISFET; The gate and source are connected to the bit line, the dummy word line, and the first dummy capacitor, and the second dummy capacitor is further connected between the source of the MISFET and the level shift signal line. semiconductor memory.