JPS6188567A - Semiconductor device - Google Patents

Abstract

PURPOSE:To equalize threshold voltage by properly selecting the directions of a plurality of FETs formed to a compound semiconductor wafer. CONSTITUTION:A semiconductor device is constituted by a GaAs wafer 1 having a face index of (110) of a main surface and a FET2 formed so that the direction of drain currents IDS runs parallel with the (1-10) axis of the GaAs wafer 1. According to such constitution, a channel region in the FET2 is difficult to be affected by piezoelectric polarization, piezo-charges, thus eliminating the dispersion of threshold voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention has a configuration that is effective for uniformizing all the characteristics when a plurality of field effect transistors are formed on a compound semiconductor wafer. Related to semiconductor devices.

[Conventional technology]

Conventionally, when a field effect transistor is formed on a GaAs wafer, a drain current is oriented to flow parallel to the <011> axis in the GaAs wafer whose main surface is a (100) plane.

This is done after the formation of the various elements is completed.
The main reason for this is that it is easy to create creases when separating the wafer into chips.

Furthermore, currently, much development and research is being carried out on integrated circuits made of compound semiconductors with the aim of putting them into practical use.
In this case, it is essential to equalize the characteristics of the field effect transistors included in the integrated circuit.

It is known that normally, when a plurality of field effect transistors are formed on a GaAs wafer, there is a large variation in the dark value voltage of each field effect transistor.

The reason for this is said to be that piezoelectric charges are generated in the channel region of the field effect transistor due to the stress between the Ga As substrate and the pannosification insulating film (Chang, M. F., et al. Appl, Ph.
ys, Lett,, vol.

45, no, 3. pp, 279-281. Aug.

1.1984>.

Figure 3 shows that when a field effect transistor is formed on a GaAs wafer whose main surface is the (100) plane so that the drain current is parallel to the <01> axis, the dark value voltage V is the thickness of the passivation insulating film. It is a diagram showing how it changes depending on thickness.

In the figure, the vertical axis represents the dark voltage V, the horizontal axis represents the gate length L9, and the thickness d of the silicon dioxide (SiOz) film, which is an insulating film for absorption, is varied.

As can be seen from the figure, when the channel becomes short, the dark value voltage Vth
has a large variation depending on the thickness d of the S i O2 film. It goes without saying that shortening the channels of this type of semiconductor device is essential for improving the degree of integration.

[Problem that the invention seeks to solve]

-m, integrated circuits using compound semiconductors are still unstable in many aspects compared to integrated circuits using silicon semiconductors.

In the above-mentioned integrated circuit, if the characteristics of the large number of field effect transistors included therein, especially the dark value voltage V, are non-uniform, the entire integrated circuit becomes inoperable.

Therefore, such products must be treated as defective products, resulting in a very low manufacturing yield.

The present invention achieves the following by selecting the direction of a plurality of field effect transistors formed on a compound semiconductor wafer throughout the period.
Efforts are being made to equalize the dark value voltage (■5).

[Failure to solve the problem]

In the semiconductor device according to the present invention, when N is an arbitrary natural number, the (N10) plane of the compound semiconductor crystal is the main surface, and the direction in which the drain current flows is <1N0>
A gate electrode, a source region, and a drain region are formed parallel to the axis.

[Effect]

With the above configuration, the dark voltage V of each semiconductor device formed on the same compound semiconductor wafer is maintained substantially constant regardless of the thickness of the passivation insulating film.

〔Example〕

FIG. 1 shows a plan view of the main parts of a semiconductor wafer at key points in the process for explaining one embodiment of the present invention. In this embodiment, N=1, and therefore the surface index of the semiconductor wafer is (110).

In the figure, 1 is Ga whose main surface has a surface index of (110).
As wafer 2, the direction of the drain current IDS is GaAs.
In the field effect transistor formed parallel to the <110> axis of the wafer 1, 2G indicates a gate electrode, 2S indicates a source region, and 2D indicates a drain region.

With such a configuration, the channel region of the field-effect transistor 2 is less susceptible to the influence of piezoelectric polarization, and hence to the influence of piezoelectric charges, and variations in the dark value voltage V are eliminated.

FIG. 2 shows a diagram for explaining the effects of one embodiment of the present invention.

In the figure, the vertical axis represents the dark voltage V, and the horizontal axis represents the thickness d of the interlayer insulating film.The solid line represents the characteristic line of one embodiment of the present invention, and the circle mark represents the conventional example. The characteristic lines of each are shown.

Gate length L of the field effect transistor from which this data was obtained
9 was set to 1.4 [μm].

As is clear from the figure, in the case of this example, no variation in the dark value voltage V occurs regardless of the thickness of the interlayer insulating film.

〔Effect of the invention〕

In the semiconductor device according to the present invention, when N is an arbitrary natural number, the semiconductor device is formed so that the (N10) plane of the compound semiconductor crystal is the main surface and the direction in which the drain current flows is parallel to the <1N0> axis. has been done.

With this configuration, all the semiconductor devices formed on the wafer are less likely to be subjected to stress engraving caused by the difference in thermal expansion coefficient between the compound semiconductor substrate and the protective film, and as a result, No piezoelectric charge is generated in the channel region due to piezoelectric polarization, and the mutual conductivity is 9. ,
Even if l is high and the channel is shortened, the dark voltage value l is maintained uniformly, so the manufacturing yield is greatly improved, and it is therefore effective in constructing compound semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of a semiconductor wafer at key points in the process for explaining one embodiment of the present invention, and FIG. The diagrams and FIG. 3 are diagrams each showing that the dark voltage of a field effect transistor changes depending on the thickness of the pansivation insulating film. In the figure, 1 is Ga whose main surface has a surface index of (110).
As wafer 2, the direction of the drain current 105 is GaAs.
In the field effect transistor formed parallel to the <110> axis of the wafer 1, 2G indicates a gate electrode, 2S indicates a source head, and 2D indicates a drain region. Patent Applicant Fujitsu Co., Ltd. Representative Patent Attorney Akio Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 2 0 0.5 1. O N repeated film thickness (7-+m) Figure 3 Lq (pm) Procedural master's letter March 15, 1985 Mr. Manabu Shiga, Commissioner of the Patent Office (Mr. Examiner of the Patent Office) 1 Display of case Showa 1959 Patent Application No. 209876 2 Name of the invention Semiconductor device 3 Relationship to the case of the person making the amendment Patent applicant Address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Fujitsu Co., Ltd. Representative Yamamoto Taku Shin 4 Agent address: 20-7, Toranomon-chome, Minato-ku, Tokyo, 171 A., N. Silicide (WSi) as a lightning electrode material (1. Name of the invention: ``Compound Semiconductor Field Effect Transistor.'' (2. Amend the claim statement to ``If N is an arbitrary natural number, the (N10) plane of the compound semiconductor crystal is the principal plane, and the direction in which the drain current flows is "A compound semiconductor heavy single-effect transistor characterized by being formed parallel to the <1N0>axis." (3) Page 1, lines 13 and 14 of the specification, "Semiconductor device '' is corrected to read ``compound semiconductor field effect transistor.'' (4) The description ``1 semiconductor wafer,'' page 5, line 1, is corrected to read ``compound semiconductor wafer.'' (5 ) The statement in the first and second lines of page 6 was changed to ``This data is based on a Schottky film made of tungsten on a GaAs wafer.
It was obtained from a barrier type field effect transistor (hereinafter referred to as MESFET). ”, he corrected. (6) The statement on page 6, line 5 of the same document has been changed to: [No change has occurred. The above explanation is for GaAs MESFETs, but the same effect can be obtained when using compound semiconductor wafers other than GaAs (e.g., InP, InGaAs, etc.). The same effect applies to a field effect transistor using an insulated gate type field effect transistor or a field effect transistor using a heterojunction (HEMT). ”, he corrected.

Claims (1)

[Claims] When N is an arbitrary natural number, the compound semiconductor crystal is formed so that the (N10) plane is the main surface and the direction in which the drain current flows is parallel to the <1@N@0> axis. Semiconductor equipment.