JPS618938A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS618938A JPS618938A JP59129266A JP12926684A JPS618938A JP S618938 A JPS618938 A JP S618938A JP 59129266 A JP59129266 A JP 59129266A JP 12926684 A JP12926684 A JP 12926684A JP S618938 A JPS618938 A JP S618938A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- elements
- wafer
- semiconductor elements
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の技術分野]
この発明は半導体素子の製造方法に関し、特に半導体ウ
ェーハに活性領域、電極等が設けられたのちの加工工程
に適用される。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and is particularly applied to a processing step after a semiconductor wafer is provided with active regions, electrodes, etc.
[発明の技術的背景とその問題点]
従来の半導体素子の製造方法(;おいて、半導体ウェー
ハに活性領域、電極等が形成されたのちに、電気的特性
測定、半導体ウェーハの薄化、粘着シートに貼着してダ
イシング、半導体素子に分割、シートから剥離等の諸工
程を経て半導体素子を得ていた。これらの諸工程を第1
図にて工程101ないし工程108に、また、第5図に
よって示す。1ず、半導体ウェーハ(以降ウェーハと略
称)の1生面に不純物拡散を施して一部の活性領域形成
、絶縁膜形成、電、極配設等を施したウェーハを出発材
料とし、これを第21!mに示す。なお−、ウエーノ為
の上面を示す第2図(a)では、このウエーノ丸に多数
整列形成されている半導体素子(11、11・・・)の
上面の電砂(lla 、 lla・・・)は図示を省略
し、同図(b)および(C)に示している。ここでウェ
ー/(1)は厚さが約600μmに形成されているので
、この厚さでは機械的強度が大きく、1だ半導体素子の
配置もマスクのアライメントに従って整列形成されてい
るので、電気的特性測定用ソケット(躯3図(ts6参
照)を順送当接させ検出された不良素子にはイン力が動
作してマーキングを施す。なお、上記ソケットは、半導
体素子主面の周辺部に形成されている電極の各々に同時
に弾接する配置に設けられた接触針((12a)第4図
)を有し、半導体素子の電極に測定電圧を印加して所定
の測定を施すようになっている。[Technical background of the invention and its problems] In the conventional manufacturing method of semiconductor devices, after active regions, electrodes, etc. are formed on a semiconductor wafer, electrical characteristics measurement, thinning of the semiconductor wafer, and adhesive Semiconductor elements were obtained through various processes such as pasting onto a sheet, dicing, dividing into semiconductor elements, and peeling from the sheet.
This is shown in steps 101 to 108 in the figure and by FIG. 1. First, a wafer in which impurity diffusion has been performed on one surface of a semiconductor wafer (hereinafter abbreviated as wafer) to form a part of an active region, an insulating film, electrodes, electrodes, etc. is used as a starting material, and this is used as a starting material. 21! Shown in m. In addition, in FIG. 2 (a) showing the upper surface of Ueno, the electric sand (lla, lla...) on the upper surface of the semiconductor elements (11, 11...) that are formed in large numbers in alignment in this Ueno circle is shown. are omitted from illustration and are shown in FIGS. 3(b) and 3(c). Here, wafer/(1) is formed to have a thickness of about 600 μm, so it has high mechanical strength, and since the semiconductor elements are arranged in line according to the mask alignment, it is electrically A socket for measuring characteristics (see Figure 3 (see TS6)) is brought into contact with the detected defective element by the input force and marked.The socket is formed on the periphery of the main surface of the semiconductor element. It has a contact needle ((12a) Fig. 4) arranged to make elastic contact with each of the electrodes at the same time, and is adapted to apply a measurement voltage to the electrodes of the semiconductor element to perform a predetermined measurement. .
次いで第1図に示す工程(103)ないし工程(108
)につき第5図を参照して説明する。Next, steps (103) to (108) shown in FIG.
) will be explained with reference to FIG.
工程103は基板(1)に研磨を施し、600μmの板
厚を200−350μmに低減させる(第5図(b))
。Step 103 is to polish the substrate (1) to reduce the board thickness from 600 μm to 200-350 μm (Fig. 5(b)).
.
工程104は基板(1)を熱可塑性の粘着テープ住4に
貼着する(第5図(C) ) 。Step 104 is to attach the substrate (1) to the thermoplastic adhesive tape 4 (FIG. 5(C)).
工程105で基板(1)にダイシングを施す(第5図(
C))。In step 105, the substrate (1) is diced (see Fig. 5).
C)).
工程106は前記粘着テープ(I7Jに貼着された基板
(1)を、この粘着テープを加熱し展張させて分割を施
す(第5図(d))。In step 106, the substrate (1) attached to the adhesive tape (I7J) is divided by heating and expanding the adhesive tape (FIG. 5(d)).
工程107は、分割されて粘着テープa湯上に粘着′
いい、工、4ワイ(II 、 11−)やや。ヶー
オ7、ら剥11mする。なお、このとき前記工程102
によってマーキングの施された半導体素子は分別される
。Step 107 is to divide the adhesive tape into pieces and stick them onto the hot water.
Good, 4-way (II, 11-) somewhat. Kao 7, Rabari 11m. Note that at this time, the step 102
Semiconductor elements with markings are sorted by the method.
[背景技術の問題点]
上記従来の方法は、ウェーハに種々の処理を施す際の割
れを防止するため、ウェーハを厚いま捷で電気的特性測
定を施すが、その後の研磨、ダイシング等の工程を経る
ので良品の半導体素子が破壊されたり、外観的に抄傷、
例えば擦過傷を受けたりなどして品質上に重大な間四が
ある。[Problems with the Background Art] In the conventional method described above, electrical characteristics are measured using thick rolls of wafers in order to prevent cracking when the wafers are subjected to various treatments, but the subsequent steps such as polishing and dicing are As the process goes through this process, good semiconductor devices may be destroyed, or the appearance may be scratched or damaged.
For example, there may be serious problems in terms of quality, such as scratches or scratches.
最近の傾向として半導体装置の小型化に伴ない半導体素
子が小型化する努力がなされている。このため、ダイシ
ング幅(隣接の半導体素子との間隔)が一般には30μ
mにとられているが、半導体素子の電気的特性測定のた
めにtI′i最少限の寸法であってこれ以上近接させる
ことは電気的特性測定が不可能であった。As a recent trend, efforts are being made to reduce the size of semiconductor elements as semiconductor devices become smaller. For this reason, the dicing width (distance between adjacent semiconductor elements) is generally 30 μm.
m, but this is the minimum dimension of tI'i for measuring the electrical characteristics of a semiconductor element, and it was impossible to measure the electrical characteristics by bringing them closer than this.
[発明の目的コ
この発明は上記従来の問題点を改良するためになされた
もので、半導体素子の小型化に対応する半導体素子の製
造方法を提供する0シ
[発明の概要]
この発明にかかる半導体素子の製造方法は、半導体ウェ
ーハに多数の半導体素子が形成されたものに対し、半導
体素子に予定される厚さまで研磨を施したのちクッショ
ン用のテープに貼着しsついでダイシング後テープを展
開し半導体素子を分割離隔させて電気的特性測定を施す
ようにしたものである。[Purpose of the Invention] This invention has been made to improve the above-mentioned conventional problems, and provides a method for manufacturing a semiconductor device that is compatible with the miniaturization of semiconductor devices [Summary of the Invention] According to the present invention The manufacturing method for semiconductor devices involves polishing a semiconductor wafer with a large number of semiconductor devices formed thereon to the desired thickness of the semiconductor device, attaching it to a cushioning tape, dicing it, and then rolling out the tape. In this method, the semiconductor element is divided and separated and the electrical characteristics are measured.
[発明の実施例コ
以下この発明の1実施例につき図面を参照して従来との
相違点について説明する。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, and its differences from the conventional one.
第6図は第1図(従来の工程図〕に準じて示す1実施例
の工程図で、その要部について実態を示す第7図と併せ
次仁述べる。なお、従来と変わらない工程については図
面に同じ符号を付けて示し説明を省略する。Fig. 6 is a process diagram of one embodiment shown in accordance with Fig. 1 (conventional process diagram), and its main parts will be described in conjunction with Fig. 7 showing the actual situation. The same reference numerals are used in the drawings, and the description thereof will be omitted.
工程101によって拡散1.電極付の完了したウェーハ
を用意し、次にこれを工程203によって所定のHす2
50〜300pmのウェーハ(2)に研磨する(第7図
(aン)0
工程204によって熱可塑性の粘着テープ(2)に貼着
する(第7図(b))。このテープには例えばT−75
0(商品型名、日東工業製)d厚さが800±100μ
mでクッション性のよいものである。Diffusion by step 101 1. A completed wafer with electrodes is prepared, and then it is heated to a predetermined H2 in step 203.
The wafer (2) is polished to a thickness of 50 to 300 pm (FIG. 7(a)) and is attached to a thermoplastic adhesive tape (2) in step 204 (FIG. 7(b)). -75
0 (product model name, made by Nitto Kogyo) d thickness is 800±100μ
m and has good cushioning properties.
ついで工程105.工程106(第7図(C) 、 (
d) )によって半導体素子に分割する。これで展開さ
れたテープ@上に離隔した半導体素子(21、21・・
・)が配列支持された状態になる。Then step 105. Step 106 (Figure 7(C), (
d) Divide into semiconductor elements by ). The semiconductor elements (21, 21...
・) becomes array-supported.
上記状態で各半導体素子に対し第3図(−)に示すよう
に、特性測定ヘッド(財)を順次位置ぎめしつつ接触さ
せて通電し電気特性のチェックを施す。なお、特性測定
ヘッド(231は第3図(b)に示すように、接触針(
23a 、 23a・・・)を半導体素子の電極(ll
a 、 lla・・・)に弾接させて測定を施すように
なつでいる。In the above state, as shown in FIG. 3(-), a characteristic measuring head is sequentially positioned and brought into contact with each semiconductor element, and the semiconductor element is energized to check its electrical characteristics. Note that the characteristic measuring head (231 is a contact needle (231) as shown in FIG. 3(b)).
23a, 23a...) as the electrodes (ll) of the semiconductor element.
a, lla...) to perform measurements.
ついで工程107により半導体素子をシートから剥離し
、工程108の半導体素子(21,2L・・)を得る0
[発明の効果]
この発明によれば、半導体素子の小型化(二適応し、ダ
イシングに可能な限りに半導体素子の電極間間隔を接近
させて形成することができる顕著な利点がある。次に、
半導体ウェーハに研磨、ダイシングを施したのちに電気
的特性を測定するので、従来の方法のように良品の半導
体素子が研磨、ダイシング等によって破損されることが
なく、半導体素子の品質の向上がはかれる利点がある。Then, in Step 107, the semiconductor element is peeled off from the sheet to obtain the semiconductor element (21, 2L...) in Step 108. There is a significant advantage that the spacing between the electrodes of a semiconductor device can be made as close as possible.Next,
Since the electrical characteristics are measured after polishing and dicing the semiconductor wafer, good semiconductor devices are not damaged by polishing, dicing, etc. as is the case with conventional methods, and the quality of semiconductor devices can be improved. There are advantages.
第1図は従来の半導体素子の製造方法の工程を示すブロ
ック図、第2図は半導体ウェーハを示し、図(a)は正
面図、図(b)は側面図、凶(c)は半導体素子の上面
図、第3図は半導体素子の電気的特性測定を説明するた
めの側面図、第4図は測定ヘッドの図、第5図(a)〜
(d)は半導体素子の製造工程の要部を示すいずれも側
面図、第6図は一実施例σノ半導ずれも@11面図であ
る。
2 半導体ウェーハ
g lla、 lla・・・ 半導体素子の
電極21 半導体素子
22 粘着テープFigure 1 is a block diagram showing the steps of a conventional semiconductor device manufacturing method, Figure 2 shows a semiconductor wafer, figure (a) is a front view, figure (b) is a side view, and figure (c) is a semiconductor element. 3 is a side view for explaining the measurement of electrical characteristics of a semiconductor element, FIG. 4 is a diagram of the measurement head, and FIGS.
(d) is a side view showing the main parts of the manufacturing process of a semiconductor element, and FIG. 6 is a side view of one embodiment of the σ semiconductor deviation. 2 Semiconductor wafer g lla, lla... Semiconductor element electrode 21 Semiconductor element 22 Adhesive tape
Claims (1)
の厚さにエッチングする工程、次に前記エッチングを施
した面を粘着シートに貼着して該ウェーハを粘着シート
に保持させる工程、前記半導体ウェーハに裁断を施し半
導体素子に分割する工程、前記粘着シートを展開させ半
導体素子を相互に離隔させる工程、前記分割された半導
体素子の電気的特性を測定する工程を特徴とする半導体
素子の製造方法。a step of etching a semiconductor wafer on which an active region, electrodes, etc. have been formed to a predetermined thickness; then a step of attaching the etched surface to an adhesive sheet to hold the wafer on the adhesive sheet; A method for manufacturing a semiconductor device, characterized by the steps of cutting and dividing into semiconductor devices, spreading the adhesive sheet to separate the semiconductor devices from each other, and measuring the electrical characteristics of the divided semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59129266A JPS618938A (en) | 1984-06-25 | 1984-06-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59129266A JPS618938A (en) | 1984-06-25 | 1984-06-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS618938A true JPS618938A (en) | 1986-01-16 |
Family
ID=15005322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59129266A Pending JPS618938A (en) | 1984-06-25 | 1984-06-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618938A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394630A (en) * | 1986-10-08 | 1988-04-25 | Rohm Co Ltd | Processing of rear of semiconductor wafer |
| JPH04367250A (en) * | 1991-06-14 | 1992-12-18 | Sharp Corp | Manufacture of semiconductor chip |
| US5523647A (en) * | 1993-03-15 | 1996-06-04 | Hitachi, Ltd. | Color cathode ray tube having improved slot type shadow mask |
| US6391679B1 (en) | 1998-11-05 | 2002-05-21 | U.S. Philips Corporation | Method of processing a single semiconductor using at least one carrier element |
| JP2009015574A (en) * | 2007-07-04 | 2009-01-22 | Murata Mfg Co Ltd | Inspection system for electromagnetic coupling module and method for manufacturing electromagnetic coupling module using the same inspection system |
| JP2009025870A (en) * | 2007-07-17 | 2009-02-05 | Murata Mfg Co Ltd | Radio ic device, inspection system thereof, and method for manufacturing radio ic device by using the inspection system |
| JP2013012209A (en) * | 2012-08-06 | 2013-01-17 | Murata Mfg Co Ltd | Inspection system of electromagnetic coupling module and method for manufacturing electromagnetic coupling module using inspection system |
-
1984
- 1984-06-25 JP JP59129266A patent/JPS618938A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394630A (en) * | 1986-10-08 | 1988-04-25 | Rohm Co Ltd | Processing of rear of semiconductor wafer |
| JPH04367250A (en) * | 1991-06-14 | 1992-12-18 | Sharp Corp | Manufacture of semiconductor chip |
| US5523647A (en) * | 1993-03-15 | 1996-06-04 | Hitachi, Ltd. | Color cathode ray tube having improved slot type shadow mask |
| US6391679B1 (en) | 1998-11-05 | 2002-05-21 | U.S. Philips Corporation | Method of processing a single semiconductor using at least one carrier element |
| JP2009015574A (en) * | 2007-07-04 | 2009-01-22 | Murata Mfg Co Ltd | Inspection system for electromagnetic coupling module and method for manufacturing electromagnetic coupling module using the same inspection system |
| JP2009025870A (en) * | 2007-07-17 | 2009-02-05 | Murata Mfg Co Ltd | Radio ic device, inspection system thereof, and method for manufacturing radio ic device by using the inspection system |
| JP2013012209A (en) * | 2012-08-06 | 2013-01-17 | Murata Mfg Co Ltd | Inspection system of electromagnetic coupling module and method for manufacturing electromagnetic coupling module using inspection system |
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