JPS6196558U - - Google Patents
Info
- Publication number
- JPS6196558U JPS6196558U JP1984181203U JP18120384U JPS6196558U JP S6196558 U JPS6196558 U JP S6196558U JP 1984181203 U JP1984181203 U JP 1984181203U JP 18120384 U JP18120384 U JP 18120384U JP S6196558 U JPS6196558 U JP S6196558U
- Authority
- JP
- Japan
- Prior art keywords
- chips
- hybrid integrated
- integrated circuit
- epoxy resin
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の混成集積回路の平面図、第２
図は第１図のＡ−Ａ′線断面図、第３図は従来の
混成集積回路の断面図である。 １…本考案による基板、２…コーテイング樹脂
、３…ＩＣチツプ、４…ＩＣチツプ、５…コーテ
イング樹脂、６…従来の基板。
図は第１図のＡ−Ａ′線断面図、第３図は従来の
混成集積回路の断面図である。 １…本考案による基板、２…コーテイング樹脂
、３…ＩＣチツプ、４…ＩＣチツプ、５…コーテ
イング樹脂、６…従来の基板。
Claims (1)
- ＩＣチツプを搭載する混成集積回路において、
ＩＣチツプをエポキシ系樹脂を介して同一位置に
搭載する、２段構造を有する混成集積回路。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984181203U JPS6196558U (ja) | 1984-11-29 | 1984-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984181203U JPS6196558U (ja) | 1984-11-29 | 1984-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6196558U true JPS6196558U (ja) | 1986-06-21 |
Family
ID=30738758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984181203U Pending JPS6196558U (ja) | 1984-11-29 | 1984-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6196558U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0888316A (ja) * | 1994-09-16 | 1996-04-02 | Nec Corp | ハイブリッドｉｃ及びその製造方法 |
-
1984
- 1984-11-29 JP JP1984181203U patent/JPS6196558U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0888316A (ja) * | 1994-09-16 | 1996-04-02 | Nec Corp | ハイブリッドｉｃ及びその製造方法 |