JPS6197869A - field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to field effect transistors, and more particularly to short channel field effect transistors (PE) with surface electronic channels.
This relates to improving the characteristics of T).

(Prior art and its problems) In a heterojunction structure having an AGaAs layer doped with a donor impurity on undoped high-purity GaAs, electrons are transferred to impurity-free GaAs as a two-dimensional electron gas.
In recent years, the electron concentration of this two-dimensional electron gas has been reduced to A A G a A
B'ET, which has a structure controlled by a Schottky gate electrode formed on the s-layer, is attracting attention as a high-frequency, high-speed device, and research and development are being actively conducted.

By the way, for these FETs, an example is JP-A-57-7.
As described in Japanese Patent No. 3979, a structure having n+ contact layers in the source and drain regions as shown in FIG. 1 has been proposed.

In FIG. 1, 11 is a semi-insulating GaAs substrate;
12 is a non-doped high purity Ga As layer, 13 and 1
4 is an n'' GaAs contact layer, 15 is a drain electrode, 16 is a source electrode, 17 is a human/GaAs@,
18 is a gate electrode, and 19 is a surface electron channel. Due to the presence of the n+ contact layer 13.14 deeper than the surface electron channel 19, the contact resistance ac of the source and drain is small, and the series resistance between the source and gate is also small, so the mutual conductance g is large. There are many advantages. However, when shortening the channel with such a structure, the high resistance G between the n+ contact layers increases.
Substrate current 20 that cannot be controlled by gate voltage in the aAs layer
is the flow.

Abnormal phenomena peculiar to short channels, such as an increase in the output conductance ga and a fluctuation in the gate threshold voltage VT, occur, and this has become a serious problem for the explosion of high-frequency devices and integrated circuits.

The above explained FgT having a heterozygous state,
A similar problem is common to FETs having a surface-closed channel, such as insulated gate FETs (MISFETs).

(Object of the Invention) The object of the present invention is to provide a short channel F which has good characteristics free from the above-mentioned abnormal phenomena without impairing the advantages of the n+ contact layer.
ETt - To provide.

(Structure of the Invention) According to the present invention, an electron layer formed on the surface of a semiconductor crystal is used as a channel, and a gate electrode that controls the channel, and a Source and drain n+ adjacent to electronic layer
In a field effect transistor comprising a contact layer and a source electrode and a drain electrode on the contact layer, the depth d measured from the electronic layer surface of the n + co/tact layer
c (μm) and conotact interlayer distance Lc (μm)/17
? d. <o, o 1s (1+12L!)
Satisfying (1) t-A field effect transistor having the characteristics can be obtained.

(Detailed explanation of configuration), 1 Hereinafter, the present invention will be explained in detail based on the drawings.

First, the basic concept of the present invention will be explained based on FIG.

′! In the structure shown in Figure s1, the thickness of the n+ contact layers 13 and 14 measured from the surface of the channel layer is ftd, and the distance between the contact layers is L6. At this time, the board current
b20 is approximately given by the following equation, considering that in the saturation region of FF and T with short channel length, the average electric field between the n+ contact layers far exceeds the threshold electric field for electron velocity saturation.

Here, ε is the dielectric constant of the semiconductor, v is the electron saturation velocity, W
is the channel width, do is the electron distribution thickness of the surface channel, and V
O2 is drain/applied voltage.

In other words, the current given by the above equation flows between the drain and source in addition to the original drain current flowing through the operating channel, and as can be seen from the fact that □b is proportional to VOS, the larger the drain voltage is.

The drain conductance gd becomes large, leading to characteristic deterioration.

Now, the drain/current ID51 of a short channel FET having one surface channel is given by the following equation, considering that electrons travel under the gate electrode at approximately the saturation speed.

l06=V, WQ5 (a) Here, QB
is the amount of charge per unit area induced at the source end of the channel by the gate voltage. In actual FET characteristics, I so
If b is about 5% or less of the drain/maximum current in the practical saturation region, there will be no practical problem.

By the way, the constants that satisfy the above conditions are for FETs with normal surface channels.

It does not depend much on the type of semiconductor material used.

Therefore, the electron charge is q, and the permittivity of vacuum is ε. If so, common to all types of F'ET, Habo Q s/ q-I X 10
” “cm-”.

'/'a=IZ5, d, -15OA, VO2-2V
(!: Consider, t is sufficient, and using these (2
)? (3) From the formula, the flexibility that d 11 and Lll should satisfy is a, <o, ox5<x+12r, H)
(4) becomes. However, here both a and La are μ
It is m'1st place.

(Example) Hereinafter, the present invention will be explained using AI! GaAs/GaAs Hetet==
An example in which the present invention is applied to an FET having a J coupling will be described.

Figure 4 shows the static characteristics of the FET in the structure shown in Figure 1 when the thickness of the n+ contact layer is large as in the conventional case. 1 shows the static characteristics of the FET according to the present invention having the structure shown in FIG. 1, when da is set to 0.05 μm. Here, both F
In ET, both = 1.5 μm, the thickness of the non-doped high purity GaAs layer 12 is 1 μm, and the n-type Al! G
The thickness of aAsff1l17 is F1500, the effective donor density is 5X 10' cm, and the gate length is 0.5 μm.

In the case of Le-0.5 μm, as is clear from equation (4).

Assuming that the dc condition is tri dc <0.06 μm, if tri dc is about 0.5 μm, the influence of the substrate current can be ignored by making d and t smaller than 600 μm.

That is, as is clear from FIG. 4 of the conventional structure and FIG. 3 of the present embodiment, the drain conductance of the static characteristics of the FET according to the present invention was extremely small compared to that of the prior art, and good saturation characteristics were obtained. Furthermore, as can be seen from the current-voltage characteristics at low drain voltages, the source-gate resistances were approximately the same value, so there was almost no increase in resistance due to decreasing d6.

Incidentally, the above-described FET according to the present invention is manufactured, for example, in the following manner. A non-doped GaAs layer and n-type A/G are formed on a semi-insulating GaAs substrate using molecular beam epitaxy (MBC).
Form aAs @, then AI! W8it-5000 was formed on the GaAs layer by sputtering.

Using a photoresist mask with a gate pattern, the WSi and A/GaAs layers are selectively etched away. Furthermore, 600 5i02 were formed using the CVD method, and the temperature was 40KeV and the dose was f12.
Through ion implantation was performed through the 8i02 film under the conditions of x1013cm→, and the SiO
After removing the two films, the ion-implanted layer other than the FET portion is removed by etching. Finally, a source electrode and a drain/* electrode are formed by a conventional method to complete the device.

Next, an embodiment of a pond according to the present invention will be described.

The fj112 diagram is an example of the pond according to the present invention. Ga
This is a schematic cross-sectional view showing the structure of PET having an As/GaAs heterojunction, and the numbers for each part are the same as in FIG. 1. This FBT is manufactured as follows.

That is, on a semi-118 green Ga-containing S substrate, an n-type/VGaAs layer t with an effective donor density L of 1 μm and an effective donor density L of 1 μm of undoped high-purity GaAs l− is formed by the MBC method.
Soo doll acid formation then A/C on GaAs1l for example
8i0 on A/GaAs1 in the part where n+ contact Nj is formed after 8i02'12000 contacts are formed by VD method.
2k: After removing the photoresist by etching using a photoresist mask, the 5i02i
The GaAs layer is removed by etching as a mask, and GaAs1 is further etched away by 800 layers. Next, for example, by a vapor phase growth method, nGa with a zero electron density lQcm is grown.
The device is completed by selectively growing AsWI to a thickness of 0.2 μm, removing the 8i02 mask, etching away the A/GaAs layer other than the FET portion, and finally forming the gate electrode and source/drain electrodes by the usual method. The gate length of the FET manufactured by the above method was α3 μm, the distance between the source n+ contact layer and the gate was 0.2 μm1, the distance between the gate and the drain n+ contact layer was 0.2 μm,
Therefore, the distance between the n+ contact layers is 0.7 μm. In this case, from equation (4), the condition that d must satisfy is d<0.
1 μm, but by setting d to -800 as in the above-mentioned example, static characteristics with extremely good saturation characteristics were obtained. As described above, since the n+ contact layer cannot be formed deeply, the present FET is characterized in that the resistance of the n+ layer is lowered by growing it on top.

The above describes an example of an F'ET with a heterojunction tW, but an F'ET with a surface channel such as a MISFET
It will be clear that the present invention is effective for all T.

(Effects of the Invention) As described above in detail, the present invention does not have the problems caused by substrate current in the prior art and has extremely good characteristics without detracting from the advantages of the n+ contact layer.
In particular, high-performance field effect transistors can be realized in short channels.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of an FET having a conventional example and a heterojunction for explaining the present invention in detail, FIGS. FIG. 4 is a diagram showing static characteristics of an embodiment of the present invention and a conventional example of the structure shown in FIG. 1, respectively. 11... Semi-insulating GaAs substrate, 12...
...Non-doped high purity GaAs layer, 13,14...
...n+ contact layer, 15...drain electrode, 16...source electrode, 17...AI
! G a As layer, 18...gate electrode. 19...Surface electron channel, 20...
Substrate current.

Claims (1)

[Claims] An electronic layer formed on the surface of a semiconductor crystal is used as a channel,
a gate electrode for controlling the channel; a source and drain n^+ contact layer formed in the semiconductor crystal in directions opposite to the gate electrode and adjacent to the electron layer; and a source electrode and a contact layer on the contact layer. In the field effect transistor comprising a drain electrode, the n^
+ Depth d of the contact layer measured from the electron layer channel surface
A field effect transistor characterized in that __c (μm) and contact layer distance L_c (μm) satisfy d_c<0.015 (1+12▲numerical formula, chemical formula, table, etc.▼).