JPS62100007A - Bias circuit in fet complementary compensation circuit - Google Patents

Abstract

PURPOSE:To eliminate an output distortion by inserting a parallel circuit comprising a DC power supply and a resistor between a source of an N-channel FET and a source of a P-channel FET. CONSTITUTION:Sources of the N-channel FET1 and the P-channel FET2 are connected via a parallel circuit consisting of a DC constant voltage source 5 having a prescribed voltage value and of a series circuit of resistors 3, 4 giving a bias voltage. An input signal Vi is fed to a gate of each FET1, 2 and an output Vo is obtained from the connecting point between the resistors 3 and 4. Thus, the relation between the input voltage and the output voltage is expressed as a linear function to eliminate the output distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bias circuit in a complementary supply circuit using FETs.

[Prior art]

FIG. 2 is a diagram showing a complementary supply circuit using a conventional N-F-Yannel junction FET and a P-channel junction FET. In the figure, 1 is an N-channel junction FET, and 2 is a P-channel junction FET. Source of N-channel junction FETI and P-channel junction F
It is connected to the source of ET2 via resistors 3 and 4, and the connection point between resistor 3 and resistor 4 is connected to the output terminal.
The base of the N-channel junction type FETI and the base of the P-channel junction type FET 2 are read directly, and one end thereof is connected to the input terminal. Note that 5 is a load resistor.

In the complementary supply circuit configured as described above, the input voltage Vi input to the input terminal is output from the output terminal as an output Vo.

[Problem that the invention seeks to solve]

However, the complementary supply circuit having the above configuration has a problem in that distortion occurs in the output as shown below due to a defect in the bias circuit that applies bias voltage to the sources of the N-channel junction type FETI and the P-channel junction type FET2.

In the circuit shown in FIG. 2 above, the drain current of FETI is set to 1. , the drain current of FET2 is Iz, the source voltage of FETI is V, , the source voltage of FET2 is v3. Resistor 5
Let the current flowing in Is be the resistance value of resistor 3.4.5, R, ++Rz+Rs, respectively, and let the drain current when the gate and source of FETI and FET2 are shorted be Lss++ID5S2. If the voltage between the source and gate of FETI and FET2 when the flow stops is V PI * V 12, then the input voltage is ■, the drain current of FETI is I, and FE T
The relationship between the drain current of 2 and 2 is as shown in the following equation.

I,=IossI/L+"(Vl VPI-Vl)"
■L=Lss2/Vr% (VIVpx
Vt)” ■As a condition for the phase compensation circuit, Ib5s+/V++”=Lssz/Vpt”=a
If 1, then "-2■ and 0 formulas become the following formulas ■ and ■.

11= a(Vi Vpt Vl)”
■I4 = a (V i Vrt Vf
)" ■Here, Vl = V, + (+/, -V0) = ■. +IIR8 V, = V. - (V = VX) = V, -IUR3 (However, Vo is an output type IE) Substitute a Niel et al. into the above formulas (7-[, L=a (Vl Vpt Vo I+R+)"
■1! = a (Vl Vpt
Vo + IJz)”
@Furthermore, from the above formulas ■ and ■, one ■. "l5Rs (V++Vr+ v.)+IR+"ffi input [1-
Issana 7: V7N〒1), but the fourth term is an irrational function, and this term does not cancel out in vo, which changes depending on any Vi, so the formula (①) is an irrational function,
The output voltage v0 will not be proportional to the input voltage V.

So-called distortion occurs.

The present invention has been made in view of the above points, and it eliminates the distortion caused by the bias circuit of the conventional complementary circuit, and provides an FET in which the output voltage is proportional to the input voltage and no distortion occurs.
It is possible to provide a complementary circuit using the following.

[Means for solving problems]

In a FET phase compensation circuit comprising an N-channel FET and a P-channel FET, a parallel circuit of a DC power supply having a predetermined voltage value and a resistor was connected between the sources of the two FETs.

[Effect]

By configuring as described above, the output voltage is accurately proportional to the input voltage, as will be explained in detail later, and no distortion occurs in the output.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a bias circuit in a FET phase compensation circuit according to the present invention. In this figure, the same reference numerals as those in FIG. N Chi■
The sources of the channel FET I and the P channel FET 2 are connected to each other via a series circuit consisting of a resistor 3 and a resistor 4 (which apply a bias voltage), and a DC constant voltage source 6 having a predetermined voltage value. In the circuit of FIG. 1, the output voltage generated across the load resistor 5 is V. , input voltage ■1, FET
The drain current of 1. , the drain current of FET2 is 1
8. FETI source 'i1 voltage is ■1, FET2 source voltage V2, current flowing through resistor 3 is il, resistor 4
The current flowing through the resistor 2 is i3, the current i8 flowing through the DC constant voltage source 6, and the resistor 3. Resistor 4. The resistance value of the resistor 5 is R, , R, , R, and the current flowing through the resistor 5 is 1. Furthermore, the drain current when the gate and source of FET and FET2 are shorted is ID5SL+Iゎ, respectively.
S! , the source-gate voltage when the drain current stops flowing are V□, ■2. Then, FETI
The drain current of 1. and the drain current of FET2 are expressed by the following equations, respectively.

L=Lss+/Vpr” (Vl-VPI-Vl)
L=Iossz/Vpz”('t/+-Vpt-Vt)
As a condition for the complementary supply circuit, if 1osst/Vpl"=Xoss*/Vpt" and this is set as a, the drain current I of FETI and FE
The drain current of T2 is I, = a (Vl-Vpr
-Vt)'<1) L=a (
Vr-Vpx-Vt>” (2
).

VO=I3R$
(3)”(i 1- iz)Rs
(4)=(I I-I z)Rs
Since (5) holds true, Vo=2aRs■, (-Vp++Vpz-(Vl-Vt
) )” a R$('V'P+ "-V, t")+
2a Rs<'/□■, -VptVz)"aRs(Vl
”Vt) (Vl-Vz) (6) Here, V+=V.+ i IRI
(7) Vt
=Vo-i tRt
(8) Also, Vl-Vx” 1 IRI+1 tRt”Vc
(9), so the above equation (19) and (
14) From the formula, i+:VcRs”VoRz/Rs(R+
"Rs) i2=VcRs-VoR+/Rs (R+"
Rz) By substituting these into the above equations (17) and (18), the following is obtained. Expressions (19), (20), and (21) are converted into (
1) Substituting into the formula and rearranging, however, A = RIR! , B = R* Rs ,
C= Rs RI, D=R+ + R2, E=
RIR! shall be.

becomes. In this equation, all terms except the first term are constants, and ■. is expressed as a linear function of the input voltage V. That is, the circuit of FIG. 1 becomes a distortion-free buffer circuit by using an N-channel FET and a P-channel FET that satisfy the conditions for a complementary supply circuit.

FIGS. 3(a) and 3(b) are circuit diagrams showing an example in which the bias circuit according to the present invention is applied to a source follower circuit using an FET.

FIG. 3(a) shows a circuit in which the bias circuit shown in FIG. 1 is placed before a source follower circuit formed by connecting the sources of an N-channel junction FET 11 and a P-channel junction FET 12. By configuring
From the above equations (10), (11), and (12), D becomes the output voltage of the source voltage V1 of the N-channel FETI and the source voltage V of the P-channel FET2. Since both relationships are expressed as linear functions of the input voltage (2), these voltages become the input terminals of the next-stage source follower, resulting in a buffer circuit with no distortion and low output impedance.

In FIG. 3(b), 14 is an N-channel MO8 type F
ET, and 15 is a P-channel MO8 type FET. The N-channel MO3 type FET14 and the P-channel M
A bias circuit shown in FIG. 1 is placed in front of the source follower circuit composed of the O8 type FETI 5. By configuring as described above, a buffer circuit with no distortion and low output int':'-dance can be obtained.

In the relational expression (12) between V and vo in the circuit of Fig. 1, %
Since it is expressed by the formula %, by extracting the difference between the drain currents of FETI and FET2 in some way, the output current ■.

= Voltage where LIz is expressed as a linear function of input voltage V -
A current converter is obtained. An example of this is shown in FIG. In the same figure, if a current I, l equal to the drain current I+ of FETI flows through the current mirror circuit 21, and a current It' equal to the drain current (■) of FET 2 flows through the current mirror circuit 22, then L=1. ', I! =L, Il"-1□'=LL, and the output current I0 is obtained. Also, the ratio of converting voltage changes into current changes can be adjusted arbitrarily by selecting the resistance value of the resistor 23 to an appropriate value. The amplification factor can be determined.

〔Effect of the invention〕

As explained above, according to the FET bias circuit according to the present invention, the relationship between the input voltage and the output voltage can be expressed by a linear function, so an output without distortion can be obtained, and it is excellent for various buffer circuits, etc. It can be expected that it will be effective.

[Brief explanation of drawings]

Figure 1 is a bias circuit diagram of the FET according to the present invention, Figure 2 is a conventional complementary circuit diagram, Figures 3 (a), (b) and 4.
Each figure is a circuit diagram to which the FET bias circuit of the present invention is applied. In the figure, 1, 11...N channel FET, 2゜12
...P f Jannel FET, 6... DC constant voltage source, 3, 4, 5, 13, 14, 15, 16.17...
・Resistor, 18...Nf Jannel MO5 type FET,
19--Pfw tunnel MO8 type FET.

Claims (1)

[Claims] A FET phase compensation circuit comprising an N-channel FET and a P-channel FET, characterized in that the sources of both FETs are connected through a parallel circuit of a DC power supply having a predetermined voltage value and a resistor. Bias circuit for FET phase compensation circuit.