JPS621027A - Cassette type magnetic tape reading controller - Google Patents

Abstract

PURPOSE:To minimize the deterioration of the CPU processing capacity and reading the serial data and the byte data out of the pulse information received from an audio CMT, by providing the CMT pulse data reception processing mode using hardware and the CMT serial data reception processing mode against the received I/O request to a magnetic tape reading controller. CONSTITUTION:The hardware which attains the CMT pulse data reception processing contains a trailing edge signal control part, an interval timer, an OR gate, a 2-bit counter and an RS flip-flop. When the CMT serial data reception processing is attained, the normal program execution of a CPU is stopped by a request produced by the CMT pulse data reception processing. Then the CPU itself carries out the CMT serial data reception processing while various states and data on the CPU are held. When this serial data reception processing is through, the CPU restarts the execution of program which is so far discontinued by the held status and data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an audio cassette magnetic tape control device that reads pulses output from a general audio cassette magnetic tape and decodes serial data.

[Conventional technology]

Audio cassette magnetic tape (hereinafter referred to as audio commercial
(referred to as T) is quite popular as an auxiliary memory for microcomputers because it is compact, easy to handle, and the device is inexpensive. Recently, this audio CMT has been widely adopted not only in the field of microcomputers but also in minicomputers, hand belt computers, etc. due to its versatility as an input medium. Due to the high versatility of audio CMT as an input medium, the interface for decoding serial data is required to have higher functionality and higher performance.

A conventional example of a microcomputer with a built-in interface for decoding the serial data of this audio CMT is shown in the second example.
This will be explained with reference to the block diagram shown in the figure, the audio CMT output pulse waveform diagrams shown in FIGS. 3 and 4, and the flowcharts shown in FIGS. 5, 6, and 7.

The conventional microcomputer 100 includes an execution unit 108,
Detecting the falling edge of the output pulse of the program memory 108, the data memory 111, and the audio CMT,
A falling edge signal control unit lO1 that outputs a falling edge signal 1011 synchronized with this, and this audio CMT.
The interrupt control section 110 notifies the execution section 108 of an interrupt using a falling edge signal 101-1, and the interrupt control section 110 is connected to each other via a data bus 117.

The execution unit 108 has a program counter 108-1, a program status word 108-2, and a general-purpose register set 108-3, reads and executes instruction codes from the program memory 108, and stores processed data in the data memory 11.
Store on 1. On the data memory 111, there is a pulse counter 111-1 that counts the number of received pulses every time a falling edge signal of a pulse output from the audio CMT occurs, and this pulse counter Ut-t.
Serial counter 111-2 counts as the number of serial data receptions each time the count for one serial data is completed.
, and each time the serial data is received, it is set to the L bit of the serial data.
a 1-byte serial data storage area 111-3 that is set and saved right-aligned from SB; a byte data storage area 111-5 that stores the 1-byte data;
It consists of a pointer 111-4 pointing to the storage address. The interval timer 102 starts counting by a timer start, sets the set value to overflow, and generates an interval overflow signal (hereinafter referred to as an interval OVF signal) using a timer section 102-2.
and the interval overflow flag (hereinafter referred to as the interval OVF signal) set by the interval OVF signal.
(referred to as VF flag) 102-3.
, after the value of this interval timer 102 is set,
Counting of the set value starts only after the start command is executed.

Next, a method of calculating a value to be set in the interval timer 102 will be explained with reference to the diagram shown in FIG. 3 which shows the format of the output pulse of the audio CMT. The logic value of the output pulse of an audio CMT is determined by the high or low frequency, and is generally “0”.
is 1200 (H2), "1" is 2400 (H2), and the number of pulses at each frequency is determined by the modulation speed. At the modulation speed of this conventional microcomputer, the logic “
The waveforms of these two pulses are called the logic "0" pulse and the logic "1" pulse, respectively. Also, the logic time of the logic "0" is 1. For example, if the period from the falling edge of time rt to the falling edge of time T3 is 2N, the logic time of logic "1" is N from the falling edge of time T1 to the falling edge of time T2.Interval timer The value to be set in 102 is obtained from the average time of the logic "0" and logic "1". Therefore, the setting value of the terpal timer 102 = -7 - = 1, 5
It becomes N. As a result, when the logical value is "0", the interval timer 102, which started when the falling edge of 1 hour T1 was detected, turns on when the interval OVF flag 102-3 is checked when the falling edge of time T3 is detected, and similarly If the logical value is "1", the interval timer 10 starts when the falling edge of time TI is detected.
2 is the interval OV when the falling edge of time T2 is detected.
When the F flag 102-3 is checked, it is turned off. Therefore, in the interrupt service by the falling edge signal 101-1 after setting the calculated average interval setting value of logic "0" and logic "1" in the interval timer 102, the start of the interval timer 102 and the interval OVF What is necessary is to execute the process of checking the flag 102-3, counting the pulses until one serial data reception is completed, and the process of resetting the interval OVF flag 102-3.

The output pulse diagram of the audio CMT in Figure 4 shows the pulse waveform when 1 byte data = "6B"H is output.
Since the byte data is output sequentially starting from the least significant bit (LSB), in the above interrupt service, ■ After receiving the pulse data for the serial data, the obtained serial data is stored in the serial data storage area t for 1 byte. t 1-
3, the bits may be set sequentially starting from the least significant bit (LSB) like the 1-byte data in FIG.

Next, with reference to the flowcharts of FIGS. 5, 6, and 7, we will explain the processing procedure of the interrupt service generated by the falling edge signal 101-1 of the audio CMT. In the memory 111, a received 1-byte serial data storage area 111-3
The byte data storage area 111-5 is set to sequentially store 1 byte of data received, and 4 is set to the initial value of the pulse counter 111-1 that counts down from the received pulse until 1 serial data is set. , the initial value of the serial counter 111-2 that counts down until the reception of 1 byte data is completed is set to 8, and the pointer 111-4 of the byte data storage area 111-5 that stores byte data every time the reception of 1 byte data is completed is set to 8. The storage address of each byte data storage area 111-5 is set in advance.

In the flowchart of FIG. 5, when the falling edge signal 101-1 of the audio CMT is input, the execution unit 1
08 executes audio CMT falling edge interrupt processing. That is, first of all, in order to hold the processing contents up to that point, the program counter 108-1, program status word 108-2, general-purpose register server)
Temporarily save the contents of 108-3 to the stack (Process 1) Next, start the interval timer 102 in which the average logical time of logic "0" and logic "1" is set (Process 2), and continue. The information of the pulse counter l1l-1, which counts down every time a falling edge occurs, is stored in the register 3), and the interval OVF flag 10.
2-3, the interval timer 102, which started during software processing of the previous falling edge interrupt, is at logic “O”.
It is set when the average logic time of logic "1" has elapsed, so if the interval OVF flag 102-3 is on, the pulses that occurred before the current falling edge interrupt occur will be set to logic "0". If the interval OVF flag 102-3 is off, it means that the pulse was a logic "1".Therefore, the register loaded with the pulse count value of the pulse counter 111-1 The register value loaded with the pulse count value of the pulse counter 1111 is counted down only once after receiving a logic "L" pulse and twice after receiving a logic "O" pulse (processes 4 to 6). If this countdown reaches O, it means that the reception of one serial data pulse is completed, and in this case, the one serial data reception completion process (process 8) shown in Figure 5 is performed, and then the return process is performed. (Processing 9). If the reception of one serial data pulse has not yet been completed, immediately return processing (Processing 9) is performed.
), in the return process (process 9), the data memory 11
1 to the register, and the updated pulse count value is saved to the pulse counter 111-1. Thereafter, the general-purpose register set 10B-3, program status word 10B-2, and program counter 108-1 are restored, and the audio CMT falling edge interrupt service is resumed.

The main program processing that was interrupted by this interrupt service continues.

FIG. 6 is a flowchart of the aforementioned one serial data reception completion process. First, the data in the serial counter i 11-2 that counts 1 byte of serial data and the serial data storage area 111-3 are read from the data memory 111 and are stored in each register (process 20).
0 Next, check the interval o F flag 102-3 and process 21). If it is on, this means that one serial data worth of logic "O" pulses has been received, and in this case, reset the carry flag. If it is off, this means that one serial data worth of logic "1" pulses has been received, and the carry flag is set (process 23).
. The register in which the data read from the serial data storage area 111-3 is set is rotated to the right together with the carry flag (process 20, whereby one serial data received this time is set to the most significant bit of the register, The serial data that has been received previously and has been set in each bit is shifted one bit lower.At this point, the next pulse is stored in the register in which the value of the pulse counter 111-1 used in the flowchart of Fig. 5 is set. In order to count the data, the initial value = 4 is set and the interval OVF flag 102-3 is reset (process 25).Then, the value of the serial counter 1112 is set to count l serial data reception. Process registers in a countdown manner 2B
), it is checked whether the value of this register has become O (process 27).

If the value of the register in which the value of the serial counter 111-2 is set is O, this means that reception of 1 byte of serial data is completed, and at this time, l, as shown in FIG.
<Perform the return process (process 29) after performing the byte data reception completion process (process 28). If the reception of 1 byte of serial data has not yet been completed, immediately perform the return process (process 28).
In the return process (process 29), which performs process 29), the registers are loaded from the data memory 111, and the serial counter 111-2 updated in the previous process and each loaded register in the serial data storage area 111-3 are loaded. Serial counter 111- of data memory 111
2 and stored in the serial data storage area 111-3. Thereafter, this serial data reception completion process merges into the pulse falling edge interrupt process shown in FIG. 6, and returns from the interrupt.

FIG. 7 is a flowchart of the 1-byte data reception completion process shown in process 28 in the explanation of FIG. 6 above. In this 1-byte data reception completion process, first, data memory 11! Pointer to the byte data storage area 111-5, which is the save destination for the 1-byte data received from t t 1
-4 is read and set in the register 30), 6th
During the process shown in the figure, the data in the register in which one byte of serial data has been set is stored in the byte data storage area 111-5 indicated by the register to which pointer 111-4 is set (31), and then the data in the register set in pointer 111-4 is stored. Update the address value of the register where the value was set, and set the initial value = 8 to the value of the register where the value of the serial counter 111-2 was set in order to count the next serial data 32) , a return process (process 34) is performed, and a return process (process 30) transfers the data in the register to which the value of the pointer 111-4 that was updated during the 1-byte data reception completion process to the pointer 111-4 of the data memory 111. Thereafter, this 1-byte data reception completion processing routine merges with the serial data reception completion processing routine shown in FIG. 6, and after the return processing (process 29) of the 1-byte data reception completion processing, As explained above, the audio CMT in the conventional microcomputer is 1 Software processing using a serial data reception interrupt normally involves processing such as pulse counting, serial data reception, 1-byte data reception, and 1-byte data storage, but in addition to this, CPU interrupt processing, Considerable overhead is involved, such as saving and restoring register sets, program counters, program status words, etc., returning to the main routine, and reading and decoding individual instructions.

[Problem that the invention seeks to solve]

This overhead occupies a considerable proportion of the entire interrupt service routine, and in addition, until the reception of one serial data is completed, interrupt processing is performed twice at logic "0", and interrupt processing is performed twice at logic "1".
Since interrupt processing is activated four times, this conventional method has a major problem in that it reduces the processing time of the main program and lowers the processing capacity of the CPU.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMT-based control device that reads serial data and byte data from pulse information received from an audio CMT while minimizing deterioration in CPU processing performance.

[Means for solving problems]

The present invention provides hardware for the processing that occurs when an audio CMT receives an input pulse, that is, the processing that checks the logical value of received pulse data a predetermined number of times and completes the reception of serial data (hereinafter referred to as CMT pulse data reception processing). After receiving 1 serial data, the software further sets the logical value of the audio CMT for 8 bits and completes the reception of 1 byte data (hereinafter referred to as CMT serial data reception processing) without any software overhead or code. This will be realized by

That is, in the cassette type magnetic tape reading control device of the present invention, the central processing unit (CPU) responds to the contents of serial data reception based on the processing request of the serial data detection section while maintaining the state related to program execution. When the serial data detecting section generates the serial data reception processing request, the serial data reception processing means causes the central processing unit to store data on a cassette-type magnetic tape. It is characterized in that it performs reception processing of input serial data in accordance with the information being received.

The hardware that realizes the CMT pulse data reception process includes a falling edge signal control section, an interval timer, an OR gate, a 2-bit counter, and an RS flip-flop, and realizes the CMT serial data reception process. In response to the request generated by the CMT pulse data reception processing, the CPU stops its normal program execution operation, and the CPU itself receives the CMT serial data while retaining the various states (hereinafter referred to as status) and data of the CPU. Since this is achieved through processing, special hardware for CMT serial data reception processing is not required. When the CPU finishes CMT serial data reception processing, the program that was suspended due to the status and data held is Resumes execution. Therefore, the interruption of the program is not visible to the software, and it appears as if the CMT serial data reception process was automatically inserted into the program.

According to the present invention, it is possible to eliminate the occurrence of an interrupt until the reception of 1-byte data of the audio CMT is completed, and it is possible to reduce the burden on software processing.

Furthermore, once the CMT serial data reception processing completes receiving 1 byte data, the next series of received data processing and the processing of the received 1 byte data are generally handled by software processing using interrupts, but when receiving from the audio CMT, If the number of data bytes is predetermined, it is possible to easily realize a predetermined number of CMT serial data reception processes by simply adding one counter and without using interrupt processing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a cassette type magnetic tape reading control device according to the present invention.

In this embodiment, a falling edge of an output pulse of an audio CMT is detected, and a falling edge signal 101-
1, and an interval timer 102 started by this audio CMT falling edge signal 1ot-i.
)-/</110VF signal 102-1,! : An OR gate 103 that takes the logical sum of the falling edge signal 101-1, a 2-bit counter 104 that counts up based on the pulse count signal 103-1 output from the OR gate 103, and an RS flip-flop that holds the interval OVF signal 102-1. pulse count O
An I10 request control unit toe that accepts a CMT serial data reception processing request based on the VF signal 104-1, an I10 request control unit 10B, a process execution request line 10B-1, and an I10 processing mode specification line 10.
A request reception unit 107 that receives B-2 and controls the operation of the execution unit, a program memory 109 that stores programs such as a main program and a serial data reception processing program, and a data memory 111 that holds processing data.
, a program counter 108-1 that holds the address of the next program to be executed, a program status word 108-2 that indicates the operating status of the entire execution section, and an arithmetic and logic unit (hereinafter referred to as ALU) that has an arithmetic and logic operation function. 11B), a general-purpose register cellar consisting of various data, pointers, etc.) 10B-3, an instruction register 113 that should hold instructions to be executed, and an instruction register 1.
an instruction decoder 114 that generates various control signals according to the contents of 13; an execution control section 115 that controls the operation of the entire execution section based on the output of the instruction decoder 114; and a terminal counter (hereinafter referred to as TC 112). TC1
12 exists in the data memory 111 and can be set to any value by software.0 In this embodiment, the TC 112, which counts down in synchronization with the pulse count OVF signal 104-1, has a count until the completion of 1-byte data reception. The value=8 is stored in advance by software.

First, CMT pulse data reception processing will be explained with reference to FIG. Falling edge signal control section 1
01 detects the falling edge of the audio CMT pulse and the high level signal of the falling edge signal 101-1 is output to the interval timer 102 and the OR gate 103. First, the OR gate 103 outputs the pulse count signal 10.
3-1 is output to the 2-bit counter 104. at the same time,
The interval timer 102 receives the falling edge signal 101-
1 starts a timer set in advance for the average logic time (= 1.5N) between logic "ON" and logic "1" of the CMT pulse data.The interval timer 102 is set by the next falling edge signal 101-1. If the overflow occurs within the set time, the interval OVF signal IQ2-1 is set to low level, and if the set time overflow occurs, the interval OVF signal 102-1 is set to high level.

It is output to the RS flip-flop 105 and the OR gate 103. OR gate 103 is interval OVF signal 10
When the counter 2-1 outputs a high level signal, it outputs a pulse count signal 103-1 to the 2-bit counter 1G4. Therefore, by the time the reception of one serial data of CMT pulse data is completed, if the logic is "L", the falling edge signal 1
01-1 is 4 times, and when the logic is "0", the falling edge signal tot-t and the interval OVF signal 102-1 are alternately sent 2 times each, for a total of 4 times, and output to the OR gate 103, and the pulse count signal 103-1 is output. is a 2-bit counter 104
will be counted up. The 2-bit counter 104 is a 2-bit counter whose initial state is "00" and which overflows at the fourth count and returns to the initial state "00", so when the reception of one serial data of CMT pulse data is completed, the logical value becomes "0". ” and “l” cause an overflow and return to the initial state “00”. When the 2-bit counter 104 overflows, it outputs the pulse count OVF signal 1G4-1 to the I10 request control unit 10B, and the RS flip-flop 105 outputs the pulse count OVF signal 1G4-1 to the I10 request control unit 10B.
Holds signal 102-1. Interval OVF signal 1
The inverted output signal 105-1 of 02-1 completes the CMT pulse data reception process by a series of processing of one or more serial data of the CMT pulse. This series of processing corresponds to the falling edge interrupt processing excluding the serial data reception completion processing (processing 8) in FIG.
Executes MT serial data reception processing.

Next, CMT serial data reception processing will be explained with reference to FIG. 1 as well. The execution unit normally transfers the instructions stored in the program memory 109 corresponding to the contents of the program counter 108-1 to the instruction register 113, and the instruction decoder 114 and execution control unit 115 perform various controls to execute the program. It has been realized.

- Each time an instruction is executed, the program counter 108
-1 is updated to the value of the address to be executed first. The I10 request reception unit 107 sends the I10 processing request line 1 every time the l instruction is completed.
Sample 0B-1 and repeat the above operation when it is low level.

Next, the behavior when a receive I10 request occurs is 9%
I'll ・to 1 0 し・L ・h
^ ・/ # 1117 J・ko I
X・II ii +l・Pulse counter OV which is an overflow signal for counting the number of pulses received for data
By outputting the F signal 104-1 to the I10 request control unit 10B, the execution unit issues an I10 request for CMT serial data reception processing. The request is accepted and the one with the highest priority is selected from among them, but this is omitted in this embodiment. The engineering 10 request control unit 10B is C
When the I10 request for MT serial data reception processing is made, the I10 processing execution request line 10B-1 and the I10 processing type designation line 10B-2 are set to high level. When the I10 request reception unit 107 detects that the I10 process execution request line 10Ei-1 is at a high level, it samples the level of the I10 process processing type designation line 10B-2. If the I10 process execution mode designation line 10B-2 is at a high level, the I10 request reception unit 107 determines that the request is a CMT serial data reception processing request, and forces the command register 113 to write the CMT
Set the serial data reception processing code. The execution control unit 115 prohibits updating of the address of the program counter 108-1, and then starts the following processing while holding the values of the program counter 108-1, program status word 108-2, and general-purpose register set 108-3. .

■ The I10 request control unit 10B sends T on the data bus 117.
C112 and the address of the serial data storage area 111-3 are output.

(2) The execution controller 115 sets the addresses of this TC 112 and the serial data storage area 111-3 in the read register.

■ The execution control unit 115 sets the TC 112 to A I, U 1
1B is used to subtract 1, and the result is stored in T C112 again.

■ Next, if the result of sampling the data output signal 105-1 is on, a carry is set, and if it is off, the carry is reset and rotated to the right along with the contents of the set register in the serial data storage area 111-3. .

■ Subsequently, the RS is set by the reset input signal 105-2.
Flip-flop 105 is reset.

The above series of processes completes the CMT serial data reception process. This series of processes corresponds to the serial data reception completion process excluding the 1-byte data reception completion process (process 28) in FIG.

In the execution unit, if the value of T C112 does not become O after the subtraction process in a series of serial data reception completion processes, the reception I
CMT serial data reception processing is executed every time 10 requests occur. However, if the value of TC112 becomes 0 after a series of subtractions during CMT serial data reception processing,
The ALU 118 automatically outputs the 1-byte data reception completion interrupt control line 11111-1 to the process 10 request control unit 106, and the I10 request control unit 1.06 sets the I10 process execution request line 10B-1 high. level, and the I10 processing type designation line 10B-2 is set to low level. The I10 request reception unit 107 determines this as a 1-byte data reception interrupt request and forcibly sets a 1-byte data reception interrupt processing code in the instruction register 113. Furthermore, the execution control unit 115 saves the program counter 10B-1 and the program status word 108-2 to the data memory 111.

The I10 request control unit 106 transfers the 1-byte data reception interrupt address onto the data bus 117, and the execution control unit 115
starts the 1-byte data reception interrupt processing program by transferring this 1-byte reception interrupt address to the program counter 108-1. In this way T C1
If the value of 12 becomes O by subtraction during CMT serial data reception processing, a 1-byte data reception interrupt request is generated at the same time as the CMT serial data reception processing ends, and 1
The series of 0 or more processes in which the byte data reception interrupt program is started corresponds to the 1-serial data reception completion process excluding the 1-byte data reception completion process (process 28) in FIG.

The 1/<ite data reception interrupt zologram executes the same process as the 1-byte data reception completion process routine in FIG. That is, after saving the registers (processing 1), data is transferred from the data memory 111 to the byte data storage area 11.
Process 30) to read the pointer 1114 of 1-5, and transfer the received 1-byte data to the byte data storage area 111.
-5 (process 31) 0th order, pointer 111-
TC112 updated with 4 and configurable via software.
Initial value = 8 to count next serial data
(Process 32) Return processing (processing 32) that restores the register contents updated by a series of program processing of 1 or more
Step 30 and return the data saved in the data memory 111 to the program counter 10B-1 and program status word 108-2, return from the 1-byte data reception completion interrupt program, and join the interrupted main program. do.

Note that in this embodiment, processing by interrupt is generated after receiving one byte data, but if the number of bytes to be output as CMT byte data is determined in advance, CMT serial data reception processing can be performed simply by providing one more counter. It is also possible to easily store the data on the data memory within the system.

〔Effect of the invention〕

As explained above, the present invention provides a cassette-type magnetic tape reading control device that performs CMT pulse data reception processing by hardware, CMT serial data reception processing format in response to a reception I10 request, and CMT serial data reception processing format based on the reception I10 request format.
By having a processing form for byte data reception interrupt requests, when CMT pulse data reception is performed by software settings in CMT pulse data reception processing and CMT serial data reception processing, it is possible to perform processing that is not inherent in conventional interrupt processing. Saving the program counter and program status word to the stack, branching to the interrupt program, reading general-purpose register set saving processing instructions, saving interrupts such as decoding, and returning general-purpose register set processing instructions. The time spent on return processing from interrupts such as reading, decoding, branch processing to the main program, program status word, and return from the program counter stack can be significantly reduced. After the 1-byte data reception is completed by the CMT serial data reception process, a 1-byte data reception interrupt request is automatically generated and the CMT serial data reception interrupt program is activated.
This makes it possible to minimize the decline in processing capacity.

As described above, the cassette type magnetic tape reading control device according to the present invention can provide the most suitable received data processing means for receiving processing of input pulses of audio CMT and receiving processing of serial data, and has practical effects. Extremely expensive.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an execution unit of an embodiment of a cassette type magnetic tape reading control device according to the present invention, and FIG. 2 is a block diagram of a conventional example of a cassette type magnetic tape reading control device.
Figure 3 is a time chart showing the logical values of output pulses of the audio CMT, Figure 4 is a pulse waveform diagram of 1-byte data "6B" output from the audio CMT, and Figure 5 is a flowchart of falling edge interrupt processing. , FIG. 6 is a flowchart of 1 serial data reception completion processing, and FIG. 7 is a flowchart of 1-byte data reception completion processing. 101: Falling edge signal control unit 1ot-t: Falling edge signal 102: Interval timer 102-1: (7turba JL/OV F signal 1
03 Nior gate 103-1: Pulse count signal 104: 2-bit counter 104-1: Pulse count OVF signal 105
: RS flip-flop 105-1 : Data output signal 105-2 : Reset input signal 108 : I10 request control unit 10B-1 : I10 processing execution request line 10Ei-2 : I10 processing processing form designation line 107
:I10 Request reception unit 108: Execution unit 108-1 Nibragram counter 108-2 Nibragram status word 108-
3: General purpose register set 109 Niprogram memory 110: Interrupt control unit 111: Data memory 111-1: Pulse counter 111-2 Niji real counter 111-3 Niji real data storage area 111-4
: Pointer 111-5 : Byte data storage area 112 : Terminal counter (TC) 113 : Instruction register 114 : Instruction decoder 115 : Execution control section 116 : Arithmetic logic unit (ALU) 11B-
1: 1 byte data reception completion interrupt control edge Figure 7

Claims (1)

[Scope of Claims] A pulse detection section detects pulses input in accordance with information recorded on a cassette-type magnetic tape, and a counting operation is started in synchronization with the pulse detection of the pulse detection section, and the a pulse period measuring section that measures the period of a pulse corresponding to information recorded on a cassette-type magnetic tape; controlled by the pulse detecting section and the pulse period measuring section;
A serial data detection section that generates a serial data reception processing request, a memory section that stores programs and various data, and a central processing unit that selectively executes processing requests of the serial data detection section and processing according to the program. In the cassette type magnetic tape reading control device, the central processing unit can perform processing corresponding to the content of serial data reception based on a processing request from the serial data detection unit while maintaining a state related to program execution. comprising serial data reception processing means, and when the serial data detection section generates the serial data reception processing request, the serial data reception processing means:
A cassette-type magnetic tape reading control device, wherein the central processing unit performs a process of receiving serial data input in correspondence with information stored on a cassette-type magnetic tape.