JPS62123767A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To protect information from being erased by floating charge by a method wherein a groove type capacitance unit is provided between the region where a memory cell unit is formed and the region where a peripheral circuit is formed to capture the floating charge. CONSTITUTION:Information is stored by a memory cell in such a manner that the information from a diffused layer 2 which is a digit line is controlled by the gate electrode 6 of a switching MIS transistor and the charge is stored in the boundary between a capacitance insulating film 10 contacted with a capacitance gate electrode 7 and a diffused layer 3. Between the region where the unit of the arranged parts 3, 7 and 10 of the memory cell is formed and a peripheral circuit, the 2nd capacitance part composed of the parts 3', 7' and 10 which has a groove type structure and whose capacitance gate electrode 7' is given the earth potential through an insulating film 4' is formed to capture the floating charge which has polarity opposite to that of the charge stored in the substrate side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device in which information is stored in a capacitor in the form of charge.

[Conventional problems]

FIG. 2 shows a cross-sectional view of a conventional MIS semiconductor memory cell having a trench-shaped capacitor, in which one electrode of the capacitor has a power supply potential.

Conventionally, the information in the diffusion layer (2), which is a digit line, was controlled by the gate electrode (6) K of the switching MIS transistor, and the information in the diffusion layer (2), which was a digit line, was controlled by the capacitive insulating film (K) in contact with the capacitive gate electrode (7).
10) and the diffusion layer (3), information is stored by accumulating charges at the interface.

[Problem that the invention seeks to solve]

In the conventional memory cell described above, when the capacitive gate electrode (7), which is one electrode of the MIS capacitor, is connected to the power supply, the surface of the P-type silicon substrate (1) facing the capacitive gate electrode in FIG. An inversion layer is formed at and serves as the other electrode of the capacitor section. In this region, from the diffusion layer (2), which is a digit line, to the gate electrode (6) of the switching transistor.
), when data with a "High" level is written, this "High" level potential is released through the substrate from elements in the periphery of the memory cell array including the memory cell of interest. There was a problem in that they were lost by absorbing the absorbed electrons.

In this case, the reason why electrons are released is that when a high potential voltage is applied to the gate electrode that forms the capacitor, such as when activating a word line, electrons are excessively accumulated in the inversion layer region that is the opposite electrode. In this case, electrons are gradually released from this inversion layer region through the substrate.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems and provide a semiconductor memory device in which information stored in the opposite electrode of the capacitor gate (7) is not erased by electrons in the substrate.

[Failure to solve the problem]

The present invention provides a semiconductor memory in which a memory cell array including an access transistor and a MIS capacitor connected to the access transistor, and a peripheral circuit of the memory cell array are integrated on a single semiconductor substrate. In the device, a groove-shaped capacitor is formed between a region where the array of memory cells is formed and a region where the peripheral circuit is formed, and the MIS capacitor constituting the memory cell is accumulated on the substrate side. A voltage is supplied to the other electrode of the groove-type capacitor such that the free charge having the opposite polarity to that of the charge is captured in one electrode of the groove-type capacitor, and the free charge is captured in the memory cell. The gist is to prevent the accumulated charge from disappearing.

〔Example〕

Examples of the present invention will be described below with reference to the drawings.
.

FIG. 1 is a sectional view showing one embodiment of the present invention.

Note that the same reference numerals are given to the same components as in the conventional example, and explanations thereof will be omitted. The difference between this embodiment and the conventional example is that in FIG. 1, the capacitor gate electrode (7' ) is at ground potential by forming a second capacitor portion having a groove-shaped structure.

As a result, according to this embodiment, even if electrons released from the periphery of the memory cell group are attracted to the target memory cell group via the substrate, the capacitor gate provided at the boundary with the memory cell group With the electrode at ground potential, an impurity diffusion layer region (3'
), which prevents the "High" level information stored in the first capacitor section from disappearing due to electrons as in the conventional case.

The second capacitor section with a groove-type structure has the ability to absorb electrons that pass deeper into the substrate than a capacitor section formed with a planar structure, so that a memory cell having a capacitor section with a planar structure is It is also effective for memory cells having trench-type capacitive parts.

〔effect〕

As explained above, according to the present invention, the groove-type capacitor provided between the memory cell and the peripheral circuit captures the free charge having the opposite polarity to the charge accumulated in the memory cell. The cell has the advantage of being able to hold information accurately.

[Brief explanation of drawings]

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 1... Pfi silicon substrate, 2, 5.6... Access transistor, 3.7
．． 10... Capacitor, 31, 7/, 10... Groove type capacitor.

Claims (1)

[Claims] In a semiconductor memory device in which a memory cell array including an access transistor and a MIS capacitor connected to the access transistor and a peripheral circuit of the memory cell array are integrated on a single semiconductor substrate, A groove-shaped capacitor is formed between a region where an array of memory cells is formed and a region where the peripheral circuit is formed, and charges accumulated on the substrate side of the MIS capacitor constituting the memory cell. 1. A semiconductor memory device characterized in that a voltage is supplied to the other electrode of the trench capacitor such that free charges of opposite polarity are captured by one electrode of the trench capacitor.