JPS62132425A - Counter - Google Patents

Abstract

PURPOSE:To simplify the test by providing a detection means whether the bit content of a counter is all 1 or all 0 and a means bringing all carry or borrow signal to each bit of the counter to 0 and 1. CONSTITUTION:Bits are supplied to a latch 1, a carry control MOS transistor (TR) 2 to the next stage, a precharge MOS TR 3 of a carry signal line 6, are a carry signal 4, a negative logic 6 of the carry signal line, a carry signal discharge control signal 7 and a carry signal 10 to the least significant bit and given to a half adder 5, an AND gate 8 detecting that the all bits of the counter are logical 1, a NOR gate 9 detecting that bits of the counter are logical 0. In case of latch test, all bit 1 or 0 is written in the latch 1, the test is conducted whether or not the level of the AND gate 8 or the NOR gate 9 is logical 1 and the carry signal 10 to the least significant bit is made inactive (1). Thus, the test is realized simply at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is employed in integrated circuit devices such as microprocessors, and particularly relates to a test circuit for a counter that performs increment and decrement operations.

[Conventional technology]

Conventionally, counters built into data processing devices such as microprocessors are tested by reading out the actual value after it has been incremented or decremented and checking whether the value matches the expected value. I was doing it.

[Problem that the invention seeks to solve]

Therefore, conventional counter testing methods require means for reading the counter value and comparing it with the expected value.

However, in recent years, due to the need for high-speed data processing, microprocessors and the like have adopted repeat instructions that repeat the same process multiple times. In this case, it is common to have a built-in counter dedicated to counting the number of repetitions. For example, when processing string data, a dedicated counter is used to count the length of a string, that is, the number of characters. The microprocessor determines the number of repetitions by setting the number of repetitions in a counter in advance, decrementing the counter each time one process is completed, and checking whether the counter's f value has reached O. There is. Therefore, in this type of counter, whether or not the count value is ``θ'' is more meaningful than the counted value, and therefore, a means for reading out the counter value to the outside is not provided.

Therefore, when testing such a counter, since the value of the counter cannot be read, the only way is to actually execute the repeat instruction and check whether the number of repeats matches the contents of the counter. Ta. However, in this case, even if the test is repeated about 16 times, the number of test patterns and the test time are very long, and it is only possible to perform a test with a flicker of texture. Furthermore, even if the configuration is such that the value of the counter can be read for testing, a control circuit for reading the counter and control for testing are required.

Also, the nth bit of the test control tit counter is 11.
Since it is necessary to assume complex cases such as whether Z>-Q // and whether or not there is a carry to that bit, the test pattern must also be extremely complicated.

[Means for solving the problem] In order to solve the problem, the present invention provides a means for detecting that the contents of the counter are all 0 or all 1, and a means for detecting that the contents of the counter are all 0 or all 1, and a means for detecting whether the contents of the counter are all 1 or all 1 or the carry or borrow signal for each bit. A means for increasing the distance to 1 m is added.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 shows an incrementing counter showing one embodiment of the present invention.

Each bit has a latch 1, a MOS transistor 2 for carry control to the next stage, a MOS transistor 3 for precharging the carry signal line 6, a carry signal 4, a half adder 5, a negative logic 6 for the carry signal line, carry signal discharge control signal 7;
AND gate 8 detects that all bits of the counter are 1, NO gate 8 detects that all bits of the counter are 0
It has an R gate 9 and a carry signal 10 to the lowest pit.

Now, when testing the counter shown in FIG. 1, it is performed as follows.

(1) Latch test: Latch 1! /c Writes all bits 1 or 1 section of all bits, and AND gate 8 or NOR gate 9 writes 1.
A test is performed to determine whether or not. For carry to the least significant bit, signal 1o is inactive % 1 //.

(11) When the latch values are all 0 and there is no carry signal to each bit: The test can be performed in the same manner as (1).

(If all 11 latch values are 1 and the carry signal to each bit sounds: Latch I K latches all 11 and activates the carry to the least significant bit. Since the latch values are all 1, The carry of each bit is conductive through the control MO8 transistor 2Fi.Therefore, the carry from each bit is all active, and the output of the counter is all bits 0.You can test with the output of NOR gate 9. .

(1v) When all latch values are 1 and there is no carry signal to each bit: All bits 1 are latched to latch 1, and the value of the counter is latched by not adding carry signal 10 to the least significant bit. All bits are 1. This can be tested with the output of gate 8 (ANI).

(■) When the latch values are all O and there is a carry signal for each bit: All bits O are latched in latch 1, and the carry signal for each bit is discharged by setting the control signal 7 to Mctip. As a result, the output of the counter is obtained as all bits are 1, so that it can be tested through the AND gate 8.

By performing the above five operations, all components of the counter can be tested easily and quickly. In addition,
A decrement counter can also be implemented in the same way.

〔Effect of the invention〕

As explained above, one aspect of the present invention is a means for converting all carry signals to each bit into multipliers, and a means for converting all the carry signals to each bit into multipliers, and all counter outputs to be
By providing a means for detecting O and O, a counter that is easy to test can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Claims (1)

[Claims] In a counter that increments and decrements numerical data used in an integrated circuit device such as a microprocessor, a detection means for detecting whether the bit contents of the counter are all "1" or all "0"; and means for setting carry or borrow signals to each bit of the counter to all 0s and all 1s.