JPS62145A - Fsk demodulation circuit - Google Patents

Abstract

PURPOSE:To attain easy and stable demodulation even when two carrier frequencies approach together by outputting the result of decision of the same level as an effective result only when the same data are obtained consecutively for a prescribed number of times set within the cycle of carrier included per bit of a binary signal. CONSTITUTION:In constituting the titled circuit that the level is decided as effective only when the data of same level is outputted three times consecutively from a ROM 31, malfunction of demodulation attended with frequency fluctuation of a signal S1 to be modulated is minimized. Thus, even when two carrier frequencies approach together, the FSK demodulation circuit demodulating easily and stably is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a circuit after an F8 for demodulating a binary signal subjected to frequency shift keying (hereinafter referred to as FSK modulation).

[Technical background of the invention]

Conventionally, analog circuits have been used as FSK demodulation circuits that demodulate FSK-modulated binary signals.

This conventional FSK demodulation circuit is shown in FIG.

In the figure, a bandpass filter 11 removes noise components from the input signal and produces a modulated signal, that is, an FSK modulated signal.
Extract the value signal. The extracted output of this filter 11 is amplified to a desired level in a gain adjustment circuit 12, then amplitude-limited by a limiter 13, and provided to a PLL circuit 14.

The output of this PLL circuit 14 is a control voltage of an internal voltage controlled oscillator, and is applied to a comparator 15.

The level of the control voltage changes depending on the frequencies of the two types of carrier waves included in the PLL circuit 140 input signal.

The comparator 15I'i determines the level of the input voltage using the threshold located at the intermediate level of the two types of control voltages obtained in this way, and converts it into a signal with binary levels of "1" and "0". Convert. This signal is waveform-shaped by a waveform shaping circuit 16 and output as a binary signal before modulation.

[Problems with background technology]

However, as mentioned above, the carrier frequency is set by the PLL circuit 1.
In analog demodulation in which a voltage signal is captured by 4, the following problem occurs when the frequencies of two carrier waves are close to each other. That is, since the frequencies of the two carrier waves are close to each other, the control voltages corresponding to each frequency are also close to each other. As a result, it becomes difficult to set the threshold value in the comparator 15. Furthermore, even if the threshold value can be set to the optimal value, demodulation malfunctions may occur if frequency fluctuations occur in the f-modulated signal due to the incorporation of noise signals, or if circuit characteristics change due to temperature changes, etc. High risk.

[Object of the invention] This invention was made to deal with the above-mentioned circumstances.
An object of the present invention is to provide an FSK demodulation circuit that can perform demodulation easily and stably even when the frequencies of two carrier waves are close to each other.

[Summary of the invention]

This invention first determines the level of the binary signal for each repetition period by measuring each repetition period of the carrier wave of the modulated signal with a counter, and then, by this determination, the determination result of the same level is determined by the above-mentioned two. The determination result for each repetition period is output as valid only when it is continuously obtained a predetermined number of times set within the number of cycles of the carrier wave included in one bit of the value signal.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. The configuration shown in FIG. 1 will be explained below with reference to FIGS. 2 and 3. In the following explanation, the frequencies of the two types of carrier waves are respectively 390 Hz and 450 Hz.
Hz and a transmission rate of 758 PS is demodulated as a representative case. In this case, each carrier wave CW, l CW, with frequencies (390Hz) and (450Hz) is a binary signal (fv
This corresponds to the "1" level and "On level" of the I4 signal).

Further, if the frequency and transmission rate of each carrier wave CW, , CW, are set as above, each carrier wave CW, , CW, per 1 bit of a digital signal is approximately 5.
2 cycles, about 6 cycles are inserted.

Now, in FIG. 1, the counter 2I receives a modulated signal (a binary signal modulated by F8Kf) 8.
The repetition period T, ,T of each carrier wave cw, *cw,
, to measure.

The counting clock signal S of the counter 2I is obtained by dividing the clock signal S applied to the terminal 23 by 16 in the frequency dividing circuit 24. Note that the clock signal 8. The frequency is set to 4.8384 MHz, for example. Therefore, this signal 8. Clock signal 8. obtained by dividing the frequency by 16. The frequency of is the carrier frequency 390
Hz, sufficiently larger than 450 Hz, each carrier wave c
The repetition period of w, , cw can be measured with high accuracy.

The counter 21 carries out each carrier wave Cw1' of the modulated signal S1.
By being reset according to the repetition period TI or ViT of ih or CWR, it is possible to measure the above-mentioned repetition period or T. In this case, the clock signal S, which serves as a reference for the counting operation of the counter 21,
is a signal completely independent from the modulated signal S. Therefore, processing is performed to synchronize the modulated signal 81 with the counting operation of the counter 21. That is, terminal 22
The variable vI4M given to , number S1 is the waveform shaping circuit 25
It is converted into a pulse signal S4 by. This pulse signal S4 is given to the shift register 26, and the clock signal 8 is obtained by dividing the frequency of the clock signal S by 4 by the frequency dividing circuit 24.
．． (see Figure 2). This results in
A clock signal S3, in other words, a pulse signal synchronized with the counting operation of the counter 210 is obtained from the shift register 26. The pulse signal outputs q, , Qt of the first and second stages of the shift register 26 are shown in FIG.

The inverter circuit 27, the NAND circuit 28, and the NOR circuit 29 output the pulse signals Q, , Qt and the clock signals 8, . Carrier wave CW using.

Or 1 or T at the repetition period of CW.

It outputs a clock signal 86 (see FIG. 2) having a period corresponding to . This clock signal S6 is given to the counter 21 as a reset signal.

As a result, by looking at the counter 21, it is possible to measure 8 or 8 in the repetition period of the carrier wave CwI or CW.

The count value S of the counter 2Z (see FIG. 2) is latched by the latch circuit 30 at the timing of the rise of the pulse signal output Q of the first stage of the shift register 26.

As a result, the count value of the counter 21 immediately before being reset is latched in the latch circuit 30.

The count value of the counter 21 is 77 for carrier wave CW1.
5 (307(f()), and the carrier wave CW.

In this case, it becomes 672 (to 2AO)). Assuming that the frequency fluctuation range of the modulated signal S1 is ±30 Hz, the effective range of the count value of each carrier CW, , CW, is 832 (340 (f()) to 720 in the case of C%V).
(In the case of 2DO (uniform) CW, 720 (2DO (ro)
) ~ a4o (280 (FO). In order to satisfy such a count value, the number of bits of the counter 21 is set to, for example, 12 bits. Of this 12-bit count value, the lower 4 bits is truncated,
Only the upper 8 bits have a count value of 8. as latch circuit 3
Latched to 0. As a result, fluctuations in the count value S due to frequency fluctuations of the modulated signal 8□ can be suppressed as much as possible. As a result, demodulation malfunctions due to frequency fluctuations of the nuclear material X signal S are reduced.

The latch data 8° of the latch circuit 30 (see Figure 2) is:
ROM,? It is given to Z as address data. R.O.
According to this address data, M31 outputs 1-bit data 8. at '0' level or '1' level.In other words, ROM31 outputs 1-bit data 8.. of '0' level or '1' level.In other words, ROM31 has address data of 34(f(
) to 2D (if it indicates a moment, 1 at the '1'' level)
Bit data 81° is output, and if it indicates 2D (b) to 28 (b), 1-bit data 810 of the '0' level is output.

The output data S1° (see FIG. 2) of R,0M3r is applied to the shift register 32, and the clock signal 8. shifted according to As mentioned above, the period of the clock signal S6 is the repetition period T of the carrier wave CW1 or CW,
Alternatively, since it indicates T, the output data S of the ROM 31. is also shifted according to this period T, or by 2.

Output Q from the first stage to the third stage of the shift register 32
A-Q O is given to a NAND circuit 33 and a NOR circuit 34. The output Y of the NAND circuit 33 is from the above output 0 to
When Qa is all “1” level, that is, ROM31
Data of "1" level 8m three times in a row. When is output, it becomes "O" level. As a result, the D flip-flop circuit 35 is preset, and its output Q becomes "1".
``The level is high.The output
That is, when the data S1° at the "0" level is output from the ROM 31 three times in a row, the level becomes a+1s.

As a result, the output Q of the D flip-flop circuit 35 is “
0" level. Also, the output Q of the shift register 32
When one or two of A to QO change from the “1” level to “0” level, the NAND circuit 33
The output Y of D flip-flop circuit 35 changes to the "1" level, but since the output X of the NOR circuit 34 remains at the "O" level, the output Q of the D flip-flop circuit 35 maintains the "1" level. If the outputs 0 to qa of the shift register 32 all change from the "1" level to one or two of them to the "1" level, the output X of the NOR circuit 34 changes to the "O" level, but the NAND circuit Since the output Y of 33 remains at the ``1n level, D
The output Q of the flip-flop circuit 35 maintains the "0" level. Thereby, the output Q of the D flip-flop 1 circuit 35 can be regarded as a demodulated output of a binary signal. However, the phase of the binary signal in this case is delayed by two cycles of the carrier wave compared to the phase of the binary signal seen from the single-role output QA of the shift register jj.

In this way, according to the configuration in which the level is determined to be valid only when data at the same level is output from the FLOM 31 three times in a row, demodulation due to frequency fluctuations of the f-modulated signal S, malfunctions can be minimized. This will be explained using FIG. In order to make the explanation easier to understand, FIG. 3 shows an example in which a modulated signal S is demodulated in which a carrier wave that includes 9 cycles per one bit of a binary signal corresponds to the "1" level of the binary signal.

Now, due to frequency fluctuations due to the mixing of noise signals, '1
Suppose that a frequency fluctuation occurs in the 5th cycle of the level bit string. In this case, if the frequency fluctuation is large, from R, 0M5r shown in FIG. As is clear, the judgment data 81G at the "0" level is output in the 5th cycle.Thus, the output Y of the NAND circuit 33 changes from the "O" level to the "1" level in the 5th cycle. As a result, the D flip-flop 1 circuit 35 is released from the preset state, but since the output X of the NOR circuit 34 remains at the 0" level, the output Q of the D flip-flop 1 circuit 35 maintains the "1" level. Therefore, the erroneous determination at the output stage of the ROM 31 is eliminated at the output stage of the D flip-flop 1 circuit 35.

Note that the continuous same level data S output from ROMar is the final level determination condition of the binary signal by the NAND circuit 33 and the NOR circuit 34. The number of outputs is set within the number of cycles of the carrier waves CW and CWt included in one bit of the binary signal. Therefore, in this embodiment, the number of cycles of transport fl cw and +ff is set to 3, which is less than 5, 2, and 6.

As described in detail above, in this embodiment, a binary signal is demodulated by digital processing in which the frequency of the carrier wave Cw1 or CW is captured by the counter 21 as a repetition period T or T. According to such a configuration, 2
Even when two carrier wave frequencies are close to each other, level determination is possible without any complicated K17M adjustment. Further, according to such a configuration, the counter 2 latches a margin for frequency fluctuation in the latch circuit 30.
1 count value 8. This can be easily selected by changing the number of bits or the judgment output of the ROM 31, so that erroneous judgments due to frequency fluctuations can be suppressed to the utmost.

In addition, in this embodiment, in the first step, the level of the bit included in the carrier wave CW or CW is determined by the counter 21 or the like every 1 or T in each repetition period of the carrier wave CW or CW. 32 etc., the level is finally judged only when the above judgment result satisfies a specific condition. According to this configuration, compared to the case where the level is determined simply by the above-mentioned first stage processing as explained in FIG. It can be reduced as much as possible.

Further, in this embodiment, since the level is determined by digital processing, there is almost no problem of erroneous determination due to fluctuations in circuit characteristics due to temperature changes or the like.

Note that the present invention is not limited to the above embodiments.

For example, in the previous embodiment, the counter 21 is
．． The repetition period T, IT of the carrier waves CW, , CWl
Although the case where the modulated signal St is synchronized with the counting operation of the counter 21 in order to reset at t has been described, it is of course possible to synchronize the counting operation of the counter 2Z with the modulated signal S8. It is.

〔Effect of the invention〕

According to the present invention, it is possible to provide a demodulation circuit for the F8 that can easily and stably demodulate a binary signal even when the frequencies of two carrier waves are close to each other.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
3 are timing charts for explaining the operation of FIG. 1, and FIG. 4 is a circuit diagram showing a conventional FSK demodulation circuit. 21... Counter, 24... Frequency dividing circuit, 25...
Waveform circular circuit: J6.32...Shift register, 2
1... Inverter circuit, 211.33... NAND circuit, 29.3.4... NOR circuit, 30... Latch circuit, 31... OM, 3s... D free lag flop circuit .

Claims (1)

[Claims] By resetting the counting operation according to each repetition period of the carrier wave of the frequency shift keyed binary signal,
a counting means for measuring the repetition period; a first level determination means for determining the level of the binary signal according to the count value of the counting means for each repetition period of the carrier wave; Only when the same level determination result is obtained consecutively a predetermined number of times determined in advance within the number of cycles of the carrier wave included in one bit of the binary signal, the first level determination means determines An FSK demodulation circuit comprising: second level determination means for validating the result and outputting a signal indicating the determined level.