JPS6214949B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly DBT.
(Depleted Base Transistor) structure semiconductor device.

Transistor elements such as vertical JFETs and SITs are being developed by actively applying the formation of a high-resistance layer and the expansion of a depletion layer in the high-resistance layer.
In SIT, a high-resistance semiconductor layer (impurity concentration: on the order of 10 ¹³ /cm ³ ) with extremely high resistance is required in order to create a so-called normally-off device by covering the channel with a depletion layer in a zero gate bias state. As a result, its production has become extremely difficult.

On the other hand, the DBT element has a structure similar to that of a vertical JFE as shown in FIG. A type region 3 is formed, and depletion layers 4 formed around this region 3 are connected to each other. Thereafter, a polycrystalline silicon layer 6 doped with an N-type impurity is formed via an insulating film 5 to serve as an emitter region, and collector, emitter, and base electrodes are taken out from each region as shown. It is a bipolar type transistor that operates with the depletion layer 4 as a base to drive current. Such DBT is also a type of normally-off device that actively utilizes the depletion layer, but since the depletion layers must be connected to each other, there are some issues such as controlling the concentration of the epitaxial layer 2 and emitter size. However, it has the disadvantage of being difficult to manufacture. Furthermore, since the depletion layer that acts as a base between the emitter region and the collector region is present on the surface of the semiconductor substrate, there is also the disadvantage that noise increases due to the influence from the surface.

An object of the present invention is to provide a semiconductor device having a transistor element using a depletion layer without strictly controlling the impurity concentration of the epitaxial layer and without being influenced by the substrate surface.

The present invention will be explained below using the drawings.

FIG. 2 is a diagram showing one embodiment of the present invention, a
is a plan view with electrodes and insulating films removed, and b is a cross-sectional view taken along line A-A' of a. In the figure, a high resistance (low impurity concentration: on the order of 10 ¹⁴ /cm ³ ) P type layer is formed on an N type low resistance semiconductor substrate 10 by epitaxial growth. Thereafter, a ring-shaped N-type region 12 is formed in this epitaxial layer by a well-known method. At this time, N type region 1
The depletion layer 13 generated around 2 mainly spreads within the low concentration P-type epitaxial layer 11, and this depletion layer 1
3 is connected to the depletion layer of the substrate 10, and the depths of the epitaxial layer 11 and the N-type region 12 are set so that the depletion layer 13 apparently reaches the substrate 10. Then, a P-type high concentration impurity region 14 for leading out an electrode is formed shallowly in the epitaxial layer 11 surrounded by the ring-shaped region 12. Therefore, the impurity region 14 has a structure in which its outer peripheral side wall is surrounded by the ring-shaped region 12.

In such a structure, the N-type substrate 10 is operated as an emitter region, the N-type ring-shaped region 12 is operated as a collector region, and the depletion layer in the opposing gap between the substrate 10 and the region 12 is operated as a base region. Therefore, the P-type impurity region 14 becomes an ohmic contact formation region for leading out the base electrode. In addition, 15
indicates an insulating film. In this way, by applying a forward bias between emitter E and base B and a reverse bias between base B and collector C, it operates as a bipolar transistor in the same way as a normal bipolar transistor, but the base The difference is that the region is a depletion layer between the collector region and the emitter region.

In particular, since the active region including the depletion layer that operates as the base is not affected by the surface of the semiconductor device, there is an advantage that no noise is generated due to this. With such a configuration, a large breakdown voltage can be obtained between the collector and the base, and as shown in the figure, the collector region 12
By providing the base electrode impurity region 14 and the base electrode impurity region 14 apart from each other, the collector-base breakdown voltage is further increased.

Note that it is sufficient that the depletion layer 13 reaches the emitter layer 10, and there is no need for it to be connected directly below the P-type region 14.

FIG. 3 is a diagram showing another embodiment of the present invention,
A is a plan view, and b is a sectional view taken along line B-B' of a. In this example, a plurality of P-type high concentration regions 14 for leading out base electrodes are surrounded by the collector region 12.
It has a structure suitable for operating as a high power device. In this case as well, the operation is based on the depletion layer between the collector region 12 and the emitter layer 10, and each base electrode region 14 is connected to the common base electrode B on the substrate surface.
This is a short-circuited configuration.

Note that the collector region 12 and impurity region 14 can be formed by a well-known method.

FIG. 4 is a diagram showing another embodiment of the present invention,
A is a plan view, and b is a sectional view taken along line C-C' of a. In this example, each of the plurality of electrode lead-out impurity regions 14 shown in FIG. 3 is shared by a single P-type diffusion region 14', and as in the example of FIG. 3, a high power element is obtained. Since the collector region 12 and the base electrode lead-out region 14' partially contact each other, it is inevitable that the base-collector breakdown voltage will be lower than that in the structure shown in FIG.

FIG. 5 is a sectional view showing another example of the present invention,
A case of an integrated circuit structure in which a plurality of transistors having a common emitter are formed in the same epitaxial layer 11 is shown. That is, in the transistor structure shown in FIG. 2, at the same time as the ring-shaped collector region 12 is formed, an N-type ring-shaped isolation region 16 is provided around the outer periphery of the region 12. At this time as well, the depletion layer 17 extending directly below the isolation region 16 reaches the emitter layer 10, while the depletion layer extending from the side surface of the isolation region 16 is not connected to the depletion layer of the collector region 12.

Therefore, the island regions insulated from each other by the isolation region 16 and the depletion layer 17 form the epitaxial layer 1.
1, and the transistors formed in the island region have separate structures having a common emitter. Of course, the structure shown in FIGS. 3 and 4 may also be applied to the example shown in FIG. 5 in order to make it a high-power device.

Further, in the above embodiments, an NPN type transistor structure has been described, but it is obvious that the present invention can be applied to a PNP type transistor structure.

As described above, according to the present invention, since the active region is not affected by the device surface, a device without surface noise can be obtained, and the device has a simple structure, which reduces the device area and is expected to improve the degree of integration. can.
Furthermore, it is possible to easily form high-power devices. In addition, since the collector layer is formed to a certain depth and the collector and emitter are connected by a depletion layer, if the depth of the collector layer is controlled, the concentration of the epitaxial layer can be reduced to an extremely low level like SIT. There is an advantage that the concentration does not need to be set, and the concentration does not need to be precisely controlled.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional DBT element, and FIG. 2 is a diagram showing one embodiment of the present invention, where a is a plan view and b is a
3 is a diagram showing another embodiment of the present invention, a is a plan view, b is a BB' sectional view of a,
FIG. 4 is a diagram showing another embodiment of the present invention, in which a is a plan view, b is a sectional view taken along line C-C' of a, and FIG. 5 is a sectional view showing another embodiment of the present invention. Explanation of symbols of main parts, 10...Emitsuta layer,
11...Epitaxial layer, 12...Collector region, 13, 17...Depletion layer, 14...High concentration impurity region for base electrode, 16...Isolation region.

Claims (1)

[Scope of Claims] 1. An emitter layer of a first conductivity type, a semiconductor layer formed on the emitter layer and having a low concentration impurity of a second conductivity type, and the second semiconductor layer formed in the semiconductor.
a highly concentrated impurity region of a conductivity type; and a collector region of the first conductivity type formed deeper than the impurity region in the semiconductor layer and surrounding sidewalls of the region at a distance, the collector region being formed around the collector region; A semiconductor device, wherein the depths of the semiconductor layer and the collector region are set such that a depletion layer reaches the emitter layer, and a base electrode is led out from the impurity region. 2. The semiconductor layer device according to claim 1, wherein the impurity region comprises a plurality of regions commonly connected by the base electrode. 3 an emitter layer of a first conductivity type, a semiconductor layer formed on the emitter layer and having a low concentration impurity of a second conductivity type, and the second semiconductor layer formed in the semiconductor.
a highly concentrated impurity region of a conductivity type; a collector region of the first conductivity type formed deeper than the impurity region in the semiconductor layer and surrounding sidewalls of the region at a distance; and a collector region of the collector region in the semiconductor layer; an isolation region of the first conductivity type formed deeper than the impurity region around the semiconductor layer and the collector region such that a depletion layer generated around the collector region and the isolation region reaches the emitter layer; Furthermore, a semiconductor device characterized in that the depth of the isolation region is set, and a base electrode is led out from the impurity region.