JPS6216471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control circuit, and more particularly to a decoder circuit that drives address lines of a memory circuit that controls memory read and write operations in a time-sharing manner. The objective is to reduce current consumption during write operations.

Conventionally, when a high-speed reading time (access time) of a memory circuit is required, the decoder circuit that drives the address line consumes a large amount of current, but when writing, the decoder circuit is required to be as fast as the access time. There are many things that are not done. Particularly in logic integrated circuits, high speed is often not required because timing is performed on the same chip.
By the way, in memory rotation, a decoder circuit is generally shared during reading and writing.
Therefore, extra power is consumed during writing.

FIG. 1 is a circuit connection diagram showing a conventional example of a decoder circuit composed of E/D type MOS transistors. 1 is a daypresion type load, 2 to 4
is a drive transistor of an enhancement type transistor. In the circuit shown in FIG. 1, the current consumption is almost determined by the mutual conductance (gm) of one load transistor.

The present invention has been made with this point in mind, and it is an object of the present invention to provide a memory control circuit that can maintain high speed during reading and suppress current consumption during writing.

According to the present invention, in a memory control circuit including a decoder circuit that drives an address line of a memory, a voltage level that is different during reading and writing is applied in series with a load transistor of a transistor logic gate constituting the decoder. A memory control circuit characterized in that a depletion field effect transistor whose gate is applied with a signal is connected to reduce current consumption during writing can be obtained.

Next, the present invention will be explained in detail using the drawings.

FIG. 2 is a circuit connection diagram showing the basic parts of the decoder circuit used in the present _invention . Field effect transistors 5 are connected in series, the drain of the load transistor 1 and the source of the depletion type transistor 5 are connected to the power supply _Vcc , and the gate of the depletion type transistor 5 is controlled. Connect to signal S. The control signal S is set to logic "1" (power supply voltage level) when the decoder circuit performs a read operation, and set to logic "0" (ground potential) when the decoder circuit performs a write operation. Here, the depletion type transistor is always in a conductive state, and the current flowing through the transistor changes depending on the gate voltage.

The mutual conductance gm is expressed as gm=2k (V _GS −V _T ), where k is a proportional constant determined by the structure of the transistor, and the current I _DS flowing through the depletion type transistor is I _DS =gm ² /4k.

Therefore, when the control signal S is logic "1", more current can be allowed to flow, and when the control signal S is logic "0", the current can be limited to a smaller amount.

FIG. 3 is a block diagram showing one embodiment of the present invention. 6 to 8 are decoder circuits whose basic form is shown in FIG. 2, and the control signal S is controlled to logic "1" and logic "0" during reading and writing, respectively. In other words, when reading information from memory cells,
High speed is maintained and current consumption is limited during writing. Furthermore, considering that normally one of the memory address lines is selected and the decoder circuit of the remaining unselected address lines becomes logic "0", the load transistor is in a conductive state and current flows.
It turns out that the invention is very effective.

FIG. 4 is a block diagram showing another embodiment of the present invention, which is effective when reading and writing from two memories alternately. That is, when the memory cell 17 is in the read state, the control signal S is set to logic "1", and when the memory cell 18 is set to the read state, the control signal S is set to logic "0", and the control signal S is set to logic "0" when the memory cell 17 is in the read state. Logic "1" is input to the S terminal of the controller to maintain high speed. Further, when one memory cell is in a read state, the other memory cell can perform a write operation.

As described above, the present invention enables high-speed reading and low current consumption, and is particularly effective when used in a logic integrated circuit having a plurality of internal memories.

[Brief explanation of the drawing]

Fig. 1 is a conventional decoder circuit, Fig. 2 is a circuit connection diagram showing the basic parts of the decoder circuit used in the present invention, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is the present invention. FIG. 3 is a block diagram showing another embodiment of the invention. Explanation of symbols, 1, 5...depression type load transistor, 2 to 4...enhancement type drive transistor, _A0 to _Ai ...address input, _Xi
... Decoder output, S ... Control signal, V _cc ... Power supply, 6 to 15 ... Decoder circuit, 9, 17, 18
...Memory cell, 16...Inverter.

Claims (1)

[Claims] 1. In a memory control circuit including a decoder circuit that drives address lines of a memory, in series with a load transistor of a transistor logic gate that constitutes the decoder, a signal with a different voltage level is applied to the gate during reading and writing. A memory control circuit characterized in that current consumption during writing is reduced by connecting depreciation field effect transistors.