JPS6216538B2 - - Google Patents

Info

Publication number
JPS6216538B2
JPS6216538B2 JP56035023A JP3502381A JPS6216538B2 JP S6216538 B2 JPS6216538 B2 JP S6216538B2 JP 56035023 A JP56035023 A JP 56035023A JP 3502381 A JP3502381 A JP 3502381A JP S6216538 B2 JPS6216538 B2 JP S6216538B2
Authority
JP
Japan
Prior art keywords
temperature
heat treatment
substrate
hours
oxygen concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56035023A
Other languages
Japanese (ja)
Other versions
JPS57167636A (en
Inventor
Kazunori Imaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56035023A priority Critical patent/JPS57167636A/en
Priority to DE8282301212T priority patent/DE3280219D1/en
Priority to EP82301212A priority patent/EP0060676B1/en
Priority to IE559/82A priority patent/IE55966B1/en
Publication of JPS57167636A publication Critical patent/JPS57167636A/en
Priority to US06/598,544 priority patent/US4597804A/en
Publication of JPS6216538B2 publication Critical patent/JPS6216538B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置製造に於ける前処理工程即
ち、半導体装置製造前の基板処理工程に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a preprocessing process in semiconductor device manufacturing, that is, a substrate processing process before semiconductor device manufacturing.

一般に半導体装置(IC LSI等の集積回路も含
む)を製造する場合、装置の特性不良に大きな影
響を与えるものにプロセスによつて誘起されるい
わゆるプロセス誘起欠陥や有害不純物(欠陥)が
ある。
In general, when manufacturing semiconductor devices (including integrated circuits such as IC LSI), there are so-called process-induced defects and harmful impurities (defects) that have a large effect on the characteristic defects of the devices.

これらの欠陥や不純物はキヤリアのライフタイ
ムを低下せしめるだけでなく、不純物拡散プロセ
スに於いて、スパイク拡散等により素子特性に重
大な悪影響を与えている。素子動作領域に於ける
これらの欠陥発生を防止するためや、有害不純物
を除去するため、シリコンウエハの内部に結晶欠
陥を故意に発生させ、そこをゲツタリングのシン
クとする方法、いわゆるイントリンシツクゲツタ
リング法(Interinsic Gettering以下IG法と称
す)等のゲツタリング方法が製造プロセスに取り
入れられている。
These defects and impurities not only reduce the lifetime of the carrier, but also have a serious adverse effect on device characteristics due to spike diffusion and the like in the impurity diffusion process. In order to prevent the occurrence of these defects in the device operating region and to remove harmful impurities, a method of intentionally generating crystal defects inside a silicon wafer and using them as sinks for gettering, so-called intrinsic gettering. A gettering method such as an interinsic gettering method (hereinafter referred to as IG method) is incorporated into the manufacturing process.

このIG法ではシリコンウエハ内部に欠陥を発
生させ、又素子動作に係るウエハ表面近傍には、
欠陥の無いデヌーデイドゾーン(Denuded Zone
以下D.Z.と称す)と呼ばれる領域を作る。即ち、
D.Z.に混入する有害不純物等を内部欠陥にゲツタ
リングせしめ素子動作に係るD.Z.を清浄化するも
のである。
In this IG method, defects are generated inside the silicon wafer, and defects are generated near the wafer surface related to device operation.
Defect-free Denuded Zone
Create an area called DZ (hereinafter referred to as DZ). That is,
This cleans the DZ related to device operation by gettering harmful impurities mixed in the DZ into internal defects.

IG効果を持つウエハとしては有効なゲツタリ
ングを可能とするためD.Z.幅は出来るだけ狭く発
生させた欠陥の密度としては出来るだけ大きく
105cm-2以上であることが好ましい。尚、上記D.
Z.幅については形成する素子によりそれぞれ異な
るものである。例えばバイポーラトランジスタの
場合5μm、MOSトランジスタの場合3μm程
度が素子動作に係る基板表面からの距離で、前記
D.Z.幅についてもそれぞれ出来るだけ狭い最適な
値を設定する。
As a wafer with IG effect, the DZ width is as narrow as possible to enable effective gettering, and the density of defects generated is as large as possible.
It is preferably 10 5 cm −2 or more. In addition, the above D.
Z. Width varies depending on the element to be formed. For example, the distance from the substrate surface related to device operation is about 5 μm for a bipolar transistor and about 3 μm for a MOS transistor.
For each DZ width, set the optimum value as narrow as possible.

現在知られているIG法についての概要につい
て以下図面を参照して説明する。
An overview of the currently known IG method will be explained below with reference to the drawings.

第1図aに示すように、初めにN2雰囲気中に
おいてシリコンウエハに1100℃、20時間程度の熱
処理を施す。
As shown in FIG. 1a, a silicon wafer is first heat-treated at 1100° C. for about 20 hours in an N 2 atmosphere.

通常のCZ法(Czochralski method)によるシ
リコンウエハでは、その内部に0.5〜2.0×1018cm
-3(ASTM規格、以下同様とする)程度の密度で
酸素が含有されており、そのメカニズム自体は末
だ公となつてはいないもののこの酸素濃度が結晶
欠陥形成の重要な要素となつていることが知られ
ている。
Silicon wafers manufactured by the normal CZ method (Czochralski method) have a surface area of 0.5 to 2.0×10 18 cm inside.
Oxygen is contained at a density of -3 (ASTM standard, hereinafter the same applies), and although the mechanism itself is still not publicly known, this oxygen concentration is an important factor in the formation of crystal defects. It is known.

ここで、1000℃以上の熱処理を施すことにより
表面近傍に於ける酸素は、矢印にて模式的に示す
ように外部へアウトデイフユージヨンされる。同
時にウエハ内部においてはウエハ形成状態(as−
grown状態)で存在していた欠陥核が消滅若しく
は固溶する。又、ここで通常のIG法に於いては
長時間の高温処理によりウエハ表面が荒れること
を防止するため、あらかじめSiO2等の保護膜を
被覆せしめている。
Here, by performing heat treatment at 1000° C. or higher, oxygen near the surface is out-diffused to the outside as schematically shown by arrows. At the same time, inside the wafer, the wafer formation state (as-
The defective nuclei that existed in the grown state) disappear or dissolve into solid solution. In addition, in the usual IG method, a protective film such as SiO 2 is coated in advance to prevent the wafer surface from becoming rough due to long-term high-temperature treatment.

次いで第1図bに示すように同じくN2雰囲中
において700〜800℃の温度による熱処理を40時間
程度施す。いわゆる低温アニールによる高密度欠
陥核の形成プロセスである。
Next, as shown in FIG. 1b, heat treatment is performed at a temperature of 700 to 800° C. for about 40 hours in the same N 2 atmosphere. This is a process of forming high-density defect nuclei by so-called low-temperature annealing.

aのプロセスで、ウエハ表面近傍の酸素につい
ては外部へアウトデイフユージヨンされているも
のの内部には酸素濃度が末だ高い状態にある。こ
こへ700〜800℃の熱処理を加えることにより該酸
素を集中させ欠陥核を構成する。
In the process a, oxygen near the wafer surface is out-diffused to the outside, but the oxygen concentration inside the wafer is still high. By applying heat treatment at 700 to 800°C, the oxygen is concentrated to form defect nuclei.

即ち、このプロセスに於いて高密度の欠陥核を
ウエハ内部にある程度増大させる。しかし、ウエ
ハ表面近傍においては前記aの高温アニールによ
り十分に酸素濃度を低め、且つ欠陥核を消滅若し
くは固溶させているため高密度の欠陥核が形成さ
れることはない。
That is, in this process, a high density of defect nuclei is increased to some extent inside the wafer. However, in the vicinity of the wafer surface, the oxygen concentration is sufficiently lowered by the high-temperature annealing in step a above, and the defect nuclei are eliminated or dissolved into solid solution, so that a high density of defect nuclei is not formed.

その後、第1図cに示すようにN2雰囲気中で
1050℃程度の熱処理を約20時間施しD.Z.を形成す
る。
Then, as shown in Figure 1c, in an N2 atmosphere.
A DZ is formed by heat treatment at about 1050℃ for about 20 hours.

再び比較的高温の熱処理を行なうことにより前
記bのプロセスで形成した高密度の欠陥核をIG
源と成り得る結晶欠陥に成長させる。高温の熱処
理下に於いて、欠陥核があらかじめ臨界サイズ以
上に大きくなつている場合欠陥に成長させること
が可能であるもののそうでない場合には、aのプ
ロセスで示したように該欠陥核は消滅若しくは固
溶してしまう。
By performing heat treatment at a relatively high temperature again, the high density defect nuclei formed in the process b above are removed by IG.
It grows on crystal defects that can be sources. Under high-temperature heat treatment, if the defect nucleus has already grown larger than the critical size, it is possible to grow it into a defect, but if not, the defect nucleus disappears as shown in process a. Or it becomes a solid solution.

又、たとえ前記bのプロセスに於いてウエハ表
面近傍に欠陥核を形成されていたとしても、この
cのプロセスでそのほとんど全ての欠陥核が消滅
若しくは固溶するためクリーンなD.Z.を得ること
ができる。
Furthermore, even if defect nuclei are formed near the wafer surface in the process b, almost all of the defect nuclei disappear or become solid solution in the process c, so a clean DZ can be obtained. .

以上の高温処理、低温処理をくり返すIG法に
ついては既に特開昭55−38098、54−157576及び
53−15764にも記載されており現実の半導体装置
の製造に於ける前処理工程として適用されようと
している。
The IG method, which repeats the above high-temperature treatment and low-temperature treatment, has already been described in JP-A-55-38098, 54-157576 and
53-15764, and is about to be applied as a pretreatment process in the actual manufacture of semiconductor devices.

しかし、前述の如く各熱処理において、それぞ
れ20〜40時間という長時間を要するため学問的研
究の結果としては十分にその効果が確認されてい
るものの、実際の工程に適用することは困難であ
る。
However, as mentioned above, each heat treatment requires a long time of 20 to 40 hours, so although its effectiveness has been fully confirmed as a result of academic research, it is difficult to apply it to actual processes.

即ち、高温の熱処理を長時間に及び施すためシ
リコン・ウエハ表面の荒れが、たとえSiO2等の
保護膜を十分に厚く形成していたとしても、かな
り生じるため、そのまま半導体装置形成の工程へ
流すわけにはいかない。
In other words, the silicon wafer surface is subject to high-temperature heat treatment over a long period of time, which causes considerable roughness on the surface of the silicon wafer, even if a sufficiently thick protective film such as SiO 2 is formed. I can't afford it.

ここでは、少なくとも一度のポリシング等の表
面処理が更に必要となり、工程の増大を招くとと
もにD.Z.幅の正確な制御が困難である。
Here, at least one surface treatment such as polishing is required, which increases the number of steps and makes it difficult to accurately control the DZ width.

又、事実上60時間以上にも及ぶ熱処理は生産性
を著しく低下させるものであり、加えてウエハの
反り又はゆがみ等をひき起こしかねない。
In addition, heat treatment that actually lasts for more than 60 hours significantly reduces productivity and may also cause warping or distortion of the wafer.

本発明の発明者は、上記従来の熱処理方法によ
る問題点を解決する昇温による結晶欠陥の成長方
法を既に提案している。
The inventor of the present invention has already proposed a method for growing crystal defects by increasing temperature, which solves the problems caused by the conventional heat treatment methods.

昇温による熱処理は、欠陥の成長時間を大巾に
短縮させるとともに効率の良いIGを行なわせる
ための薄いD.Z.を制御良く形成することが可能で
ある。
Heat treatment by increasing temperature can significantly shorten the growth time of defects and also form thin DZs with good control for efficient IG.

該昇温による結晶欠陥の成長に於いて、昇温速
度とD.Z.の幅とは密接な相関関係を有している。
その相関関係を酸素濃度が1.8×1018cm-3のシリコ
ン基板について第3図に示す。横軸は昇温速度
(℃/min)、縦軸はD.Z.幅(μm)を示す。
In the growth of crystal defects due to the temperature increase, there is a close correlation between the temperature increase rate and the width of the DZ.
The correlation is shown in FIG. 3 for a silicon substrate with an oxygen concentration of 1.8×10 18 cm −3 . The horizontal axis shows the temperature increase rate (°C/min), and the vertical axis shows the DZ width (μm).

ここで、最低温値は750℃、最高温値は1100℃
で、最高温値で30分の熱処理を施した結果であ
る。、昇温速度を高めるにつれD.Z.幅は増大する
傾向がある。500℃乃至900℃の低温から950℃乃
至1300℃の高温への昇温で昇温速度が5℃/
min.より遅い場合、前述の低温アニールと同様
欠陥核の高密度化が酸素のアウトデイフユージヨ
ン並びに欠陥核の消滅若しくは固溶よりも主に進
行する。又5℃/min〜14℃/minの昇温速度で
は5℃/min以下の場合程は欠陥核及び欠陥形成
に効果がないものの、所望の効果が得られる。従
つて欠陥形成には14℃/min以下の昇温速度が有
効となる。
Here, the minimum temperature value is 750℃ and the maximum temperature value is 1100℃
This is the result of heat treatment for 30 minutes at the highest temperature value. , the DZ width tends to increase as the heating rate increases. When heating from a low temperature of 500℃ to 900℃ to a high temperature of 950℃ to 1300℃, the temperature increase rate is 5℃/
If the annealing temperature is lower than min., densification of defect nuclei mainly proceeds rather than out-diffusion of oxygen and disappearance or solid solution of defect nuclei, similar to the aforementioned low-temperature annealing. Further, at a heating rate of 5° C./min to 14° C./min, the desired effect can be obtained, although it is not as effective on defect nuclei and defect formation as when it is 5° C./min or less. Therefore, a temperature increase rate of 14° C./min or less is effective for defect formation.

前述のように効率良くゲツタリングを行なわせ
るためにはD.Z.の幅が出来るだけ狭いことが望ま
しいものの特に1.5×1018cm-3以上の酸素濃度を有
する基板においては5℃/min以下の昇温速度で
は結晶欠陥が素子動作に係る基板表面近傍にまで
現れるため実際の製造工程に適用することが困難
である。
As mentioned above, in order to perform gettering efficiently, it is desirable that the width of the DZ be as narrow as possible, but especially for substrates with an oxygen concentration of 1.5×10 18 cm -3 or higher, the heating rate should be 5°C/min or less. However, it is difficult to apply this method to actual manufacturing processes because crystal defects appear near the surface of the substrate, which is involved in device operation.

本発明は、IG効果を効率よく行なえる結晶欠
陥の成長方法を提供するものだが、特に1.5×
1018cm-3以上の酸素濃度を有する基板に制御良く
薄いD.Z.を短時間で形成することを目的としてい
る。
The present invention provides a method for growing crystal defects that can efficiently produce the IG effect, and in particular,
The purpose is to form a thin DZ in a well-controlled manner in a short time on a substrate with an oxygen concentration of 10 18 cm -3 or higher.

又、前記本発明の目的は、950℃以上の熱処理
を10分以上施し、その後14℃/min以下の昇温速
度で1回以上の熱処理をくり返すことにより達成
される。特に薄いD.Z.を得るためには、該昇温速
度を少なくともその1回目に於いて5℃/min.
以下とすることが望ましい。また1.5×1018cm-3以
下の酸素濃度を有する基板においては5℃/min
以下の昇温速度で熱処理すればD.Z.が形成され、
十分なゲツタリング効果が得られる。しかし多く
ある基板の中にはD.Z.内にも単一の欠陥が形成さ
れ素子劣化を生じることがある。
Further, the object of the present invention can be achieved by performing heat treatment at 950° C. or higher for 10 minutes or more, and then repeating the heat treatment one or more times at a temperature increase rate of 14° C./min or lower. In order to obtain a particularly thin DZ, the heating rate should be 5°C/min at least in the first time.
The following is desirable. In addition, for substrates with an oxygen concentration of 1.5×10 18 cm -3 or less, 5°C/min
If heat treatment is performed at the following temperature increase rate, DZ will be formed,
A sufficient gettering effect can be obtained. However, in many types of substrates, a single defect may be formed even within the DZ, causing device deterioration.

本発明は、IG効果を効率よく行なえる結晶欠
陥の成長方法を提供するものだが、特に0.5〜2.0
×1018cm-3の酸素濃度を有する基板に制御よく薄
いD.Z.を短時間で形成することを目的としてい
る。
The present invention provides a method for growing crystal defects that can efficiently produce IG effects.
The purpose is to form a thin DZ in a well-controlled manner in a short time on a substrate with an oxygen concentration of ×10 18 cm -3 .

又、前記本発明の目的は950℃乃至1300℃の熱
処理を10分乃至10時間施し、その後500℃乃至900
℃の低温で0時間乃至15時間の熱処理を行い、次
いで500℃乃至900℃の低温から950℃乃至1300℃
への昇温を14℃/min以下の昇温速度で1回以上
の熱処理をくり返すことにより達成される。特に
よりゲツタリング効果を得るためには該昇温速度
を少なくともその1回目に於いて5℃/min以下
とすることが望ましい。さらに1.5×1018cm-3以下
の酸素濃度を有する基板においては同様950℃乃
至1300℃の熱処理を10分乃至10時間施し、該低温
処理を2時間乃至15時間の熱処理を行い、次いで
500℃乃至900℃の低温から950℃乃至1300℃への
昇温を5℃/min以下の昇温速度で1回以上の熱
処理をくり返すことにより達成される。
Further, the object of the present invention is to perform heat treatment at 950°C to 1300°C for 10 minutes to 10 hours, and then heat treatment at 500°C to 900°C.
Heat treatment for 0 to 15 hours at a low temperature of 500°C to 900°C to 950°C to 1300°C.
This is achieved by repeating the heat treatment one or more times at a temperature increase rate of 14°C/min or less. In particular, in order to obtain a better gettering effect, it is desirable that the temperature increase rate be 5° C./min or less at least in the first time. Further, for a substrate having an oxygen concentration of 1.5×10 18 cm -3 or less, heat treatment at 950°C to 1300°C is performed for 10 minutes to 10 hours, the low temperature treatment is performed for 2 hours to 15 hours, and then
This is achieved by repeating the heat treatment one or more times in which the temperature is raised from a low temperature of 500°C to 900°C to 950°C to 1300°C at a temperature increasing rate of 5°C/min or less.

即ち、前述のように昇温速度が遅いほど幅の薄
いD.Z.を形成することが可能であるが、特に酸素
濃度の高い基板の場合あまりに昇温速度を遅くす
ると素子動作に係る表面近傍にまで結晶欠陥が折
出するため、又低い酸素濃度の基板の場合、D.Z
内に存在する単一欠陥をさらに低減させるため、
あらかじめ950℃乃至1300℃の熱処理を施し基板
表面近傍の欠陥核の消滅及び欠陥核を形成する酸
素のアウトデイフユージヨンを行うものである。
In other words, as mentioned above, the slower the heating rate, the thinner the DZ can be formed, but especially in the case of a substrate with a high oxygen concentration, if the heating rate is too slow, crystals may form near the surface, which is critical for device operation. DZ
In order to further reduce single defects within
Heat treatment is performed at 950° C. to 1300° C. in advance to eliminate defective nuclei near the substrate surface and to out-diffusion oxygen that forms defective nuclei.

以下、本発明の実施例について説明を加える。 Examples of the present invention will be explained below.

第2図は該実施例の時間と温度との関係を示
す。
FIG. 2 shows the relationship between time and temperature for this example.

aで例えば1100℃の温度で60分間の熱処理をシ
リコン基板に施す。この高温処理により基板の表
面近傍の欠陥核は消滅若しくは固溶する。同時に
該表面近傍に存在する欠陥核形成の要因となる酸
素分子をアウトデイフユージヨンする。
In step (a), heat treatment is performed on the silicon substrate at a temperature of, for example, 1100° C. for 60 minutes. This high-temperature treatment eliminates or dissolves defect nuclei near the surface of the substrate. At the same time, oxygen molecules that are present in the vicinity of the surface and cause defect nucleation are out-diffused.

ここで、該熱処理の温度としては950℃以上で
なければ基板表面近傍を十分に清浄化することが
困難である。又1300℃以上になると、基板に与え
る熱の影響があまり大きくなり過ぎ、ウエハの反
り等をひき起こすことから望ましくない。
Here, unless the temperature of the heat treatment is 950° C. or higher, it is difficult to sufficiently clean the vicinity of the substrate surface. Further, if the temperature exceeds 1300°C, the influence of heat on the substrate becomes too large, which is undesirable as it may cause warping of the wafer.

第4図は1.8×1018cm-3の酸素濃度を持つ基板に
1100℃の高温熱処理を行つた場合の処理時間と
D.Z.幅の関係を示す図である。
Figure 4 shows a substrate with an oxygen concentration of 1.8×10 18 cm -3.
Processing time when performing high temperature heat treatment at 1100℃
FIG. 3 is a diagram showing the relationship between DZ widths.

この図より明らかなように熱処理時間としては
10分以上の熱処理を施すことにより効果が得られ
るが、60分程度行なえば十分である。D.Z.幅は薄
い程ゲツタリング効果があるが80μm程度の幅も
効果が確認されており、熱処理時間としては10時
間程度までは本目的に対して効果がある。
As is clear from this figure, the heat treatment time is
The effect can be obtained by applying heat treatment for 10 minutes or more, but approximately 60 minutes is sufficient. The thinner the DZ width, the better the gettering effect, but a width of about 80 μm has also been confirmed to be effective, and a heat treatment time of up to about 10 hours is effective for this purpose.

更に、基板表面保護のため、表面に二酸化シリ
コン(SiO2)等の保護膜を形成した上で本発明の
熱処理を開始することが好ましいが、この高温ア
ニールの処理中に雰囲気を酸化のものとし基板表
面にSiO2膜を形成することが可能である。尚、
該保護膜としてのSiO2膜は通常のCVD
(Chemical Vapor Deposition)法も形成可能で
あるものの、表面清浄化から直接基板自体を酸化
せしめて、形成することが好ましい。
Furthermore, in order to protect the substrate surface, it is preferable to form a protective film such as silicon dioxide (SiO 2 ) on the surface before starting the heat treatment of the present invention. It is possible to form a SiO 2 film on the substrate surface. still,
The SiO 2 film as the protective film is a normal CVD film.
(Chemical Vapor Deposition) method is also possible, but it is preferable to directly oxidize the substrate itself after surface cleaning.

上記第2図aでの高温処理終了後例えば第2図
bで示すように一旦約650℃にまで温度を低下せ
しめる。かかる降温処理は、本発明の実施に大き
な影響を与えることがないため直接基板を炉から
取り出して冷却を行なつてもさしつかえない。
After the high temperature treatment shown in FIG. 2a is completed, the temperature is once lowered to about 650 DEG C., for example, as shown in FIG. 2b. Since such temperature-lowering treatment does not significantly affect the implementation of the present invention, the substrate may be directly taken out of the furnace and cooled.

次いで、第2図cで650℃程度の熱処理を施
す。熱処理時間としては0〜15時間程度で十分で
ある。本発明による結晶欠陥の成長は主に前記a
の高温処理と、後に施す昇温工程により行なわれ
るため、ここでの低温処理は必ずしも必要ではな
い。しかし、基板によつては、特に1.5×1018cm-3
以下の酸素濃度をもつ基板にはこの低温処理を行
なうことにより内部の欠陥核の高密度化を行ない
優れた特性を示すものである。
Next, heat treatment is performed at approximately 650°C as shown in Figure 2c. A heat treatment time of about 0 to 15 hours is sufficient. The growth of crystal defects according to the present invention is mainly caused by the above-mentioned a.
The low-temperature treatment here is not necessarily necessary because it is performed by the high-temperature treatment and the temperature-raising step performed later. However, depending on the substrate, especially 1.5×10 18 cm -3
By performing this low-temperature treatment on a substrate having an oxygen concentration below, the density of internal defect nuclei is increased, and excellent characteristics are exhibited.

第2図dで2℃/min.の昇温速度で、前記650
℃から1100℃までの熱処理を行なう。
At a heating rate of 2°C/min. in Fig. 2d, the 650°C
Heat treatment is performed from ℃ to 1100℃.

本発明による結晶欠陥の成長方法では、この最
初の昇温工程により、そのD.Z.がほぼ決定される
ものである。通常の1.5×1018cm-3以上の比較的酸
素濃度の高い基板の場合5℃/min.以下の昇温
速度で約10〜30μmのD.Z.が制御良く形成され
る。D.Z.幅の設定については、前述のように素子
動作領域に欠陥が形成されない限り薄いことが好
ましく、昇温速度も出来るだけ遅くする。
In the crystal defect growth method according to the present invention, the DZ is almost determined by this first temperature raising step. In the case of a substrate with a relatively high oxygen concentration of 1.5×10 18 cm -3 or more, a DZ of about 10 to 30 μm can be formed in a well-controlled manner at a heating rate of 5° C./min. or less. Regarding the setting of the DZ width, it is preferable that the DZ width be as thin as possible unless defects are formed in the device operating region as described above, and the temperature increase rate should be as slow as possible.

以上、従来の如く初めに5℃/min.以下の昇
温速度で1.5×1018cm-3以上という高い酸素濃度の
基板に熱処理を施した場合、素子動作に係る表面
付近にまで結晶欠陥が形成されたが、又1.5×
1018cm-3以下という低い酸素濃度の基板に対して
はD.Z.内に単一欠陥が形成されることがあつたが
本発明によれば初めに950℃以上の熱処理を行な
つているためそのようなことがない。
As described above, when a substrate with a high oxygen concentration of 1.5×10 18 cm -3 or more is first heat-treated at a heating rate of 5°C/min or less as in the past, crystal defects may occur near the surface where device operation is concerned. Formed, but also 1.5×
Single defects were sometimes formed in the DZ for substrates with low oxygen concentrations of 10 18 cm -3 or less, but according to the present invention, heat treatment is first performed at 950°C or higher, which eliminates this problem. There is no such thing.

次いで第2図eで上昇された1100℃程度の温度
を約30分間保持する。かかる高温での保持は本発
明において低温時と高温時の温度差が非常に僅か
である場合以外には特に必要としない。これは第
2図gで示す低温部での保持についても同様のこ
とが言える。
Next, the temperature increased to about 1100° C. in FIG. 2e is maintained for about 30 minutes. In the present invention, holding at such a high temperature is not particularly necessary unless the temperature difference between the low temperature and the high temperature is very small. The same can be said of the holding in the low temperature section shown in FIG. 2g.

即ち、本発明では低温部においては500〜900℃
好ましくは550〜850℃、高温部において950〜
1300℃好ましくは1000〜1300℃の温度サイクルを
くり返すことにより効果が得られるが、低温部で
600℃以上、高温部で1000℃以下の場合には、前
記の如き温度を一定に保持する工程が必要とな
る。
That is, in the present invention, the temperature in the low temperature section is 500 to 900°C.
Preferably 550-850℃, 950-850℃ in high temperature section
The effect can be obtained by repeating a temperature cycle of 1300℃, preferably 1000 to 1300℃, but
If the temperature is 600° C. or higher and 1000° C. or lower in the high-temperature section, a step to maintain the temperature constant as described above is required.

次いで、第2図fで1100℃から650℃まで再び
温度を下降させる。かかる降温工程においても結
晶欠陥の成長は行なわれるものの、昇温工程ほど
の効果は得られないため特にその降温速度を限定
しなくても良い。
Then, the temperature is lowered again from 1100°C to 650°C in FIG. 2f. Although crystal defects grow in such a temperature-lowering step, the effect as great as that in the temperature-raising step is not obtained, so there is no need to particularly limit the temperature-lowering rate.

次いで、第2図gで650℃の温度を約30分程度
保持するが前述のように、かかる工程は本発明に
おいて、特に必要とするものではない。
Next, as shown in FIG. 2g, the temperature of 650° C. is maintained for about 30 minutes, but as mentioned above, such a step is not particularly necessary in the present invention.

次いで、第2図hで昇温を開始する。 Next, temperature increase is started in FIG. 2h.

本発明においては1〜3℃/min.の昇温速度
の場合該昇温工程を約2回、3〜5℃/min.の
場合約3回又5℃/min乃至14℃/minの昇温速
度ではさらに昇温をくり返すことにより十分な欠
陥成長を行なうことが可能であるが基板によつて
その回数は一定ではない。
In the present invention, the heating step is carried out approximately twice when the heating rate is 1 to 3°C/min, approximately three times when the heating rate is 3 to 5°C/min, or approximately 3 times when the heating rate is 5°C/min to 14°C/min. Regarding the temperature rate, it is possible to achieve sufficient defect growth by repeating the temperature increase, but the number of times is not constant depending on the substrate.

又、前述の如くD.Z.幅の設定には第1回目の昇
温工程における昇温速度が大きく係つており、工
程短縮から2回目以降の昇温速度又は降温速度を
14℃/min.の範囲で、十分に大きくとることが
可能である。
In addition, as mentioned above, the temperature increase rate in the first temperature increase process is largely related to the setting of the DZ width, and the temperature increase rate or temperature decrease rate from the second time onwards is influenced by the shortening of the process.
It is possible to set the temperature sufficiently within the range of 14°C/min.

以上、実施例からも明確になつたように、本発
明による熱処理では1.5×1018cm-3以上の高濃度の
酸素を含有するシリコン基板の表面近傍に制御良
く、5℃/min.以下の昇温工程でD.Z.を形成する
ことが可能である。又、本発明では特に5℃/
min.以下の昇温速度のみに適用可能ではなく、
14℃/min.以下の昇温速度であればその基板表
面近傍に欠陥核を形成せず、内部に十分なゲツタ
リング機能を有する結晶欠陥を従来に比べ非常に
短時間で成長させることができる。
As has been made clear from the examples above, in the heat treatment according to the present invention, the heat treatment in the vicinity of the surface of a silicon substrate containing a high concentration of oxygen of 1.5×10 18 cm -3 or more is performed at a rate of 5°C/min. or less. It is possible to form a DZ in a temperature raising process. In addition, in the present invention, especially at 5°C/
It is not only applicable to heating rates below min.
If the heating rate is 14° C./min. or less, defect nuclei will not be formed near the substrate surface, and crystal defects with sufficient gettering function can be grown inside in a much shorter time than conventional methods.

更に、酸素濃度が1.5×1018cm-3よりも低い基板
では、D.Z.は形成され難いが本来目的としている
シリコン表面の清浄化には上記1.5×1018cm-3以上
の高濃度の酸素濃度の基板の場合と同様一応の効
果が得られる。
Furthermore, DZ is difficult to form on a substrate with an oxygen concentration lower than 1.5 × 10 18 cm -3 , but for the original purpose of cleaning the silicon surface, a high oxygen concentration of 1.5 × 10 18 cm -3 or higher is required. As with the case of the substrate, a certain effect can be obtained.

又、該低濃度の基板で、制御良くD.Z.を形成す
る場合は、第2図cでの低温処理時間を長くする
ことが有効であり、例えば650℃で2時間以上の
熱処理を施せば良い。
Furthermore, when forming a DZ in a well-controlled manner on a low-concentration substrate, it is effective to lengthen the low-temperature treatment time shown in FIG.

従つて、本発明は酸素濃度を特に限定するもの
ではないが、しかし乍ら実用性を考慮に入れると
短時間で処理することの可能である1.5×1018cm-3
以上の酸素濃度を有する基板の適用が好ましい。
Therefore, the present invention does not particularly limit the oxygen concentration, but taking practicality into consideration, it is possible to process in a short time at 1.5×10 18 cm -3
It is preferable to use a substrate having an oxygen concentration higher than or equal to the above.

又、通常の結晶欠陥の成長に係る熱処理に於い
ては、酸化性雰囲気中よりも、窒素等、非酸化性
雰囲気中での実施が優れた結果を得られることが
知られており、本発明においても、保護膜として
のSiO2膜形成後は、炉内の雰囲気を非酸化性の
ものとすることが好ましい。
In addition, it is known that in heat treatment related to the growth of normal crystal defects, superior results can be obtained when carried out in a non-oxidizing atmosphere such as nitrogen, rather than in an oxidizing atmosphere. Also, after forming the SiO 2 film as a protective film, it is preferable that the atmosphere in the furnace be non-oxidizing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a乃至cは従来の熱処理による結晶欠陥
成長時の基板断面図を、第2図は本発明における
熱処理の温度と時間の関係を示す図、第3図は本
発明の昇温速度とD.Z.幅の関係を示す図、第4図
は本発明の基板に1100℃の高温熱処理を行う場合
の処理時間とD.Z.幅の関係を示す図である。
Figures 1a to 1c are cross-sectional views of the substrate during crystal defect growth by conventional heat treatment, Figure 2 is a diagram showing the relationship between temperature and time of heat treatment in the present invention, and Figure 3 is a diagram showing the temperature increase rate and temperature of the present invention. FIG. 4 is a diagram showing the relationship between the processing time and the DZ width when the substrate of the present invention is subjected to high temperature heat treatment at 1100°C.

Claims (1)

【特許請求の範囲】 1 シリコン半導体基板を用いる半導体装置製造
の前処理工程に於いて、酸素濃度が1.5×1018cm-3
以上を有する基板に対して950℃乃至1300℃の熱
処理を10分以上10時間以下施し、その後550℃乃
至850℃の低温で0時間乃至15時間の熱処理を行
い、次いで550℃乃至850℃の低温から950℃乃至
1300℃の高温への昇温を14℃/min以下の昇温速
度で1回以上の熱処理を行ない該基板内部に結晶
欠陥を形成する工程を有することを特徴とする半
導体装置の製造方法。 2 前記昇温による熱処理に於ける昇温速度を、
少なくとも1回目の熱処理について5℃/min以
下とすることを特徴とする特許請求の範囲第1項
記載の半導体装置の製造方法。 3 シリコン半導体基板を用いる半導体装置製造
の前処理工程に於いて、酸素濃度が1.5×1018cm-3
以下を有する基板に対して950℃乃至1300℃の熱
処理を10分以上10時間以下施し、その後550℃乃
至850℃の低温で2時間乃至15時間の熱処理を行
い、次いで550℃乃至850℃の低温から950℃乃至
1300℃の高温への昇温を5℃/min以下の昇温速
度で1回以上の熱処理を行うことを特徴とする半
導体装置の製造方法。
[Claims] 1. In the pretreatment process for manufacturing a semiconductor device using a silicon semiconductor substrate, the oxygen concentration is 1.5×10 18 cm -3
The substrate having the above is subjected to heat treatment at 950℃ to 1300℃ for 10 minutes to 10 hours, then heat treated at a low temperature of 550℃ to 850℃ for 0 to 15 hours, and then at a low temperature of 550℃ to 850℃. From 950℃ to
1. A method of manufacturing a semiconductor device, comprising the step of forming crystal defects inside the substrate by performing heat treatment one or more times to raise the temperature to a high temperature of 1300° C. at a temperature increasing rate of 14° C./min or less. 2 The temperature increase rate in the heat treatment by temperature increase,
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least the first heat treatment is performed at a temperature of 5° C./min or less. 3. In the pretreatment process for manufacturing semiconductor devices using silicon semiconductor substrates, the oxygen concentration is 1.5×10 18 cm -3
A substrate having the following is subjected to heat treatment at 950℃ to 1300℃ for 10 minutes to 10 hours, followed by heat treatment at a low temperature of 550℃ to 850℃ for 2 hours to 15 hours, and then at a low temperature of 550℃ to 850℃. From 950℃ to
A method of manufacturing a semiconductor device, comprising performing heat treatment at least once to a high temperature of 1300°C at a temperature increasing rate of 5°C/min or less.
JP56035023A 1981-03-11 1981-03-11 Manufacture of semiconductor device Granted JPS57167636A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56035023A JPS57167636A (en) 1981-03-11 1981-03-11 Manufacture of semiconductor device
DE8282301212T DE3280219D1 (en) 1981-03-11 1982-03-10 METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT WITH GLOWING A SEMICONDUCTOR BODY.
EP82301212A EP0060676B1 (en) 1981-03-11 1982-03-10 A method for the production of a semiconductor device comprising annealing a silicon wafer
IE559/82A IE55966B1 (en) 1981-03-11 1982-03-11 A method for the production of a semiconductor device comprising annealing a silicon wafer
US06/598,544 US4597804A (en) 1981-03-11 1984-04-12 Methods of forming denuded zone in wafer by intrinsic gettering and forming bipolar transistor therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56035023A JPS57167636A (en) 1981-03-11 1981-03-11 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57167636A JPS57167636A (en) 1982-10-15
JPS6216538B2 true JPS6216538B2 (en) 1987-04-13

Family

ID=12430454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56035023A Granted JPS57167636A (en) 1981-03-11 1981-03-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57167636A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437922A (en) * 1982-03-26 1984-03-20 International Business Machines Corporation Method for tailoring oxygen precipitate particle density and distribution silicon wafers
JPH01312840A (en) * 1988-06-10 1989-12-18 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS57167636A (en) 1982-10-15

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