JPS62181521A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the power consumption at an operation and a pattern area by constituting only a NAND circuit having at least two driver TRs to two transistor (TR) groups respectively comprising an N-channel MOS TR and a P-channel MOS TR and generating a pulse at every inversion of an input signal by a few TRs. CONSTITUTION:Two TRs groups comprising N-channel MOS TRs Q20, Q22, Q26, Q27 and P-channel MOS TRs Q21, Q23, Q24, Q25 whose drains sources and gates are connected mutually and whose drains and gates are connected are provided and a NAND circuit having 2 driver TRs is provided, and the sources of respective TRs group are connected to the gates of a different driver TR of the NAND circuit at every group. In inputting opposite signals to the drains of the MOS TRs of respective TRs group, since the charging and discharging times of the TR groups differ at the inversion of the input signal, a pulse is generated as the output signal of the NAND circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device configured with complementary MO8 (CMO8) transistors, and in particular to a semiconductor device used as a circuit that detects the inversion of an input signal and generates a Noculus. Regarding equipment.

[Conventional technology]

For example, in semiconductor memory devices, the speed of operation is increased by using an i4 pulse signal generated every time an address signal is inverted. In Figure 3,
An example of the configuration of this type of conventional pulse generation circuit will be shown. In the figure, Ql, Q3. Q5. Q7. QB
, Qll, Ql2. Ql3. Ql4 is P channel MOS
The transistors are shown, Q2, Q4.

Q6. Q9. Q10. Ql5. Ql6. Ql7 indicates an N-channel MOS transistor. Further, 1 indicates a power source.

When a signal a as shown in Fig. 4(,) is added to the dart of the first stage inverter as an input signal of the three-stage inverter composed of transistors Q1 to Q6, the output of the final stage inverter is shown in Fig. 4(b). An inverted signal of the input signal a as shown in FIG. At this time, due to the delay caused by each inverter, the signal A is actually inverted with a little delay compared to the signal a. This pulse generating circuit utilizes this delay as described below. That is, these signals a t
b is next composed of transistors Q7 to Q10.
It is input to the R circuit. At this time, as described above, when the input signal a is inverted from "L" to "H", the signal is delayed and inverted from "H" to "L", so the transistor Q
9. If any of the QIO is in the ON state, NOR
The output signal C of the circuit is maintained at the "L" state.

On the other hand, when input signal a is inverted from ``H'' to ``L'', the signal is delayed and inverted from ``L'' to ``H'', so both signals aeb become ``L'' by the delay time, and the NOR circuit The output signal cII'i"H". After the delay, when the signal becomes 1H'', the output signal C returns to ``L'', and as a result, a noise as shown in FIG. 4(e) is generated.

Next, transistor Q12. Q14. Q16. Q17 constitutes a circuit that performs a NAND operation on the signal a and the signal A, and the transistor Q11. Q13. Q15 constitutes a NOR circuit that outputs a signal as shown in FIG. 4(d).

First, considering a NAND circuit of signal a and signal S, when input signal a is inverted from "L" to "H", signal S is delayed and changes from "■" to "L", and signal Cは′L
Since the state is maintained at ``, the signal level becomes 1L''. After the delay, the signal C returns to 7H' and the a4 pulse is generated because the signal C is also in the L'' state. On the other hand, when the input signal a is inverted from "H" to "L", the signal A is delayed and changes from 6L" to H", and the transistor Q16. Q1
7 is in the OFF state, and the transistor Q12
．． One of Q14 is in the ON state. At this time, transistor Q11. which receives signal C as input. Q13. The part consisting of Q15 is used to output an inverted signal of signal C.
When the output signal is turned on, an error occurs.

In this way, every time the input signal a is inverted, a signal is obtained as the output signal. Note that the elbow width is determined by the delay time of three stages of inverters constituted by transistors Q1 to Q6, and can be controlled by arranging an appropriate odd number of stages of inverters.

[Problem that the invention seeks to solve]

Since the conventional P44 pulse generator circuit is composed of a large number of transistors as described above, it consumes a large amount of power during operation, and when the turn arrangement is repeated, the turn area becomes large. there were.

This invention was made in order to solve the widespread problem, and it is an object of the present invention to obtain a noise generating circuit that can configure the circuit with a small number of transistors, reduce power consumption during operation, and reduce the main turn area. With the goal.

[Means for solving problems]

The semiconductor device according to the present invention includes two transistor groups each consisting of an N-channel MO8 transistor and a P-channel MO8 transistor whose drains, sources, and darts are interconnected, and whose drains and darts are connected to each other. The NAND circuit includes a NAND circuit having driver transistors, and the sources of each transistor group are connected to the darts of different driver transistors of the NAND circuit for each group.

[Effect]

By inputting contradictory signals to the drains of the transistor groups (MOS) of each transistor group, a pulse is generated as the output signal of the NAND circuit because the charging time and discharging time of the transistor group are different when the input signal is inverted. .

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart showing its operation.

In FIG. 1, Q20. Q22. Q26. Q27 Hiro N
Channel MOS transistors are shown, Q21. Q23゜Q24. Q25 represents a P-channel MOS transistor.

1 is a power source.

The input signals a and & are contradictory signals as shown in FIG.
'', N-channel MOS transistor Q2
Since it is connected to the gate 11 drain of 0'L
'', the transistor Q20 becomes OFF, and is discharged by the P-channel MOS transistor Q21, which is connected in the same way as the transistor Q20, and the source signal e gradually becomes '' as shown in FIG. 2(e). L"
becomes. This discharge time can be increased by reducing the mutual conductance of transistor Q21. Further, the input signal a is inverted from "L" to "H", but the source signal e, which was in the "L" state at this time, is charged through the entire N-channel MOS transistor Q22 that is in the ON state, and the second As shown in Figure (d), the charging time becomes H''. This charging time can be shortened by increasing the mutual conductance of the transistor Q22. Note that at this time, the P-channel MOS transistor Q23 is in the OFF state.

In this way, by lengthening the discharging time on the one hand and shortening the charging time on the other hand, in relation to the threshold voltage Vp of the P-channel MOS transistor and the threshold voltage Vn of the N-channel MOS transistor, Q
Two inputs of the NAND circuit consisting of 27 e r 8
There is a period when both are "H". At this time, the output signal f of the NAND circuit, which is normally "H", becomes "L" and a pulse is generated.

Conversely, if input signal a changes from "L" to "H', input signal a changes from 'L' to 'H'.
When inverting from "H" to "L", voltages and pulses can be generated in exactly the same way.In this case, an N-channel MOS transistor is used to shorten the charging time of the signal e and lengthen the discharging time of the signal e. The mutual conductance of Q20 is P
Channel MO8) It is necessary to make the transconductance of the channel MO8 larger than the transconductance of the resistor Q23.

In this way, every time the input signal is inverted, a signal as shown in FIG. 2(e) is obtained as the output signal f of the NAND circuit.

Although an example in which the circuit is constructed using only MOS transistors has been described above, a capacitor may be inserted between the signal line where the signal e + 6 is generated and the ground terminal to adjust the pulse width.

〔Effect of the invention〕

As explained above, the semiconductor device of the present invention does not only include a NAND circuit having at least two driver transistors in two transistor groups consisting of an N-channel MOS transistor and a P-channel MOS transistor, but also a small number of transistors. A circuit can be constructed that generates a pulse every time the input signal is inverted. therefore,
The power consumption during operation can be reduced, and the cross section and turn area can be reduced, making it suitable for high integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing its operation, FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a timing chart showing its operation. Q20. Q22. Q26. Q27...N channel M
OS) transistor, Q21. Q23. Q24. Q25・
...P-channel MOS transistor.

Claims (1)

[Claims] A semiconductor device consisting of a complementary MOS transistor circuit formed on a semiconductor substrate, which includes two transistor groups consisting of an N-channel MOS transistor and a P-channel MOS transistor, and also includes a NAND circuit having at least two driver transistors. , the drains, gates, and sources of the N-channel MOS transistors and P-channel transistors of each transistor group are interconnected, and the drains and gates are connected to each other, and the sources are connected to the gates of different driver transistors of the NAND circuit for each group. A semiconductor device connected to