JPS62184591U - - Google Patents
Info
- Publication number
- JPS62184591U JPS62184591U JP7162386U JP7162386U JPS62184591U JP S62184591 U JPS62184591 U JP S62184591U JP 7162386 U JP7162386 U JP 7162386U JP 7162386 U JP7162386 U JP 7162386U JP S62184591 U JPS62184591 U JP S62184591U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- circuit
- vertical synchronization
- integration circuit
- signal separation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 claims description 2
- 230000010354 integration Effects 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図及び第２図は夫々本考案回路の一実施例
の回路図及び信号波形図、第３図及び第４図は夫
々従来回路の一例の回路図及び信号波形図である
。
１……複合同期信号入力端子、５……波形成形
回路、６……垂直同期信号出力端子、７……第１
積分回路、８……ピークホールド回路、９……第
２積分回路、Ｒ１，Ｒ２′……抵抗、Ｃ１′，Ｃ
１″，Ｃ２′……コンデンサ、ＤＺ……ツエナー
ダイオード、Ｄ……ダイオード。
1 and 2 are a circuit diagram and a signal waveform diagram of an embodiment of the circuit of the present invention, respectively, and FIGS. 3 and 4 are a circuit diagram and a signal waveform diagram of an example of a conventional circuit, respectively. 1...Composite synchronization signal input terminal, 5...Waveform shaping circuit, 6...Vertical synchronization signal output terminal, 7...First
Integrating circuit, 8...Peak hold circuit, 9...Second integrating circuit, R1 , R2 '...Resistor, C1 ', C
1 ″, C 2 ′... Capacitor, DZ... Zener diode, D... Diode.
Claims (1)
の積分回路を介して垂直同期信号を分離し取出す
垂直同期信号分離回路において、該積分回路の次
段にピークホールド回路を設けてなる垂直同期信
号分離回路。 A vertical synchronization signal separation circuit that separates and takes out a vertical synchronization signal via an integration circuit for removing a horizontal synchronization signal from a composite synchronization signal, the vertical synchronization signal separation circuit comprising a peak hold circuit at the next stage of the integration circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7162386U JPH0334796Y2 (en) | 1986-05-13 | 1986-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7162386U JPH0334796Y2 (en) | 1986-05-13 | 1986-05-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62184591U true JPS62184591U (en) | 1987-11-24 |
| JPH0334796Y2 JPH0334796Y2 (en) | 1991-07-23 |
Family
ID=30914341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7162386U Expired JPH0334796Y2 (en) | 1986-05-13 | 1986-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0334796Y2 (en) |
-
1986
- 1986-05-13 JP JP7162386U patent/JPH0334796Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0334796Y2 (en) | 1991-07-23 |
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