JPS62190861A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62190861A JPS62190861A JP61034659A JP3465986A JPS62190861A JP S62190861 A JPS62190861 A JP S62190861A JP 61034659 A JP61034659 A JP 61034659A JP 3465986 A JP3465986 A JP 3465986A JP S62190861 A JPS62190861 A JP S62190861A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- region
- semiconductor device
- emitter region
- darlington
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/641—Combinations of only vertical BJTs
- H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置、詳しくは、ダーリントン結合の
複数トランジスタの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly to a Darlington coupled multiple transistor structure.
従来の技術
従来、オーディオ用ダーリントン・トランジスタは、縦
電流を少なくするために、ＰＮＰ／ＮＰＮ トランジス
タの電流増幅率を同じ値のものにする方式が取られてい
た。2. Description of the Related Art Conventionally, audio Darlington transistors have adopted a system in which the current amplification factors of PNP/NPN transistors are made to have the same value in order to reduce the longitudinal current.
発明が解決しようとする問題点
しかし上述の方式では、ダーリントン・トランジスタの
ため、電流増幅率が大きく、同じ値にすることが、困難
であり、また同じ電流増幅率でも周波数が高くなると、
第２図の特性図のように、実動作のクロスオーバ一時に
、縦電流が増加するという問題点があった。Problems to be Solved by the Invention However, in the above method, the current amplification factor is large due to the Darlington transistor, and it is difficult to maintain the same value.Also, even with the same current amplification factor, as the frequency increases,
As shown in the characteristic diagram of FIG. 2, there is a problem in that the longitudinal current increases at the time of crossover in actual operation.
本発明は、上述の従来例にみられた問題点の解消をはか
る半導体装置を実現するものである。The present invention realizes a semiconductor device that solves the problems seen in the above-mentioned conventional example.
問題点を解決するための手段
本発明は、ダーリントン結合された複数トランジスタの
うち、前段トランジスタにそのエミッタ領域を囲んで、
同エミッタ領域と同導電型の分離領域を有し、この分離
領域を同一トランジスタのベース電極に結線したもので
ある。Means for Solving the Problems The present invention provides a structure in which, among a plurality of Darlington-coupled transistors, a front-stage transistor is surrounded by its emitter region.
It has the same emitter region and an isolation region of the same conductivity type, and this isolation region is connected to the base electrode of the same transistor.
作 用
本発明によると、ダーリントン・トランジスタの前段ト
ランジスタにおいては、エミッタ領域を囲むように、形
成された分離エミッタ領域のベース電極に対向した部分
をベース電極と結線したことにより、前段トランジスタ
は、スイッチング時間の一部である蓄積時間ｔｓが短か
くなる。この特性により、オーディオの実動作時に周波
数が変化しても、蓄積時間ｔｓが短かいため、クロスオ
ーバ時の縦電流が少なく押えられる。またＰＮＰ／ＮＰ
Ｎの電流増幅率の差が大きい場合も、蓄積時間ｔｓが短
かいため、縦電流は小さく押える事が可能であり、電流
増幅率の許容範囲を大きくすることができる。According to the present invention, in the front-stage transistor of the Darlington transistor, the part facing the base electrode of the separated emitter region formed so as to surround the emitter region is connected to the base electrode, so that the front-stage transistor can perform switching. The accumulation time ts, which is a portion of time, becomes shorter. Due to this characteristic, even if the frequency changes during actual audio operation, the storage time ts is short, so the longitudinal current at crossover can be kept small. Also PNP/NP
Even when the difference in the current amplification factor of N is large, the accumulation time ts is short, so the longitudinal current can be kept small, and the allowable range of the current amplification factor can be widened.
実施例 つぎに本発明を実施例により詳しく述べる。Example Next, the present invention will be described in detail with reference to examples.
第１図は本発明実施例半導体装置の断面図である。Ｎ型
シリコン基板１上にＰ型ベース領域２を形成する、次に
エミッタ領域３を形成するに際し、エミッタ領域３を囲
むように分離エミッタ領域４゜５を同時に形成する。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. When a P-type base region 2 is formed on an N-type silicon substrate 1 and then an emitter region 3 is formed, an isolated emitter region 4.degree. 5 is simultaneously formed to surround the emitter region 3.
その後エミッタ電極６．ベース電極７．コレクタ電極８
．内部配線９を形成する。またこの際にベース電極７は
、分離エミッタ領域５と結線する。Then emitter electrode 6. Base electrode7. Collector electrode 8
．． Internal wiring 9 is formed. Also, at this time, the base electrode 7 is connected to the separated emitter region 5.
なお、表面には絶縁＠１ｏを設けている。Note that insulation @1o is provided on the surface.
この実施例構造によると、ダーリントン・トランジスタ
の蓄積時間ｔｓを短かくすることができる。これは、領
域６をベース電極７と結線することにより領域５．同２
．および同１で構成される寄生トランジスタが部分的に
動作し、スイッチングオフ時に寄生トランジスタを介し
て電流が流れるため、蓄積時間が短かくなるという利点
がある。According to the structure of this embodiment, the storage time ts of the Darlington transistor can be shortened. This is achieved by connecting region 6 to base electrode 7. Same 2
．． Since the parasitic transistor composed of the transistors 1 and 1 partially operates and current flows through the parasitic transistor when switching off, there is an advantage that the storage time is shortened.
また後段トランジスタ内の領域４は同トランジスタ破壊
耐量の向上にのみ動作する。後段トランジスタは回路構
成上、蓄積時間は存在しないので、領域５と同様な結線
にする必要はない。Further, the region 4 in the subsequent transistor operates only to improve the breakdown resistance of the transistor. Since there is no storage time in the latter stage transistor due to its circuit configuration, it is not necessary to use the same connection as in region 5.
本発明は、上記実施例半導体装置に限られるものではな
く、種々の変形あるいは応用が可能である。たとえば実
施例ではＮＰＮダーリントン・トランジスタについて説
明したが、ＰＮＰダーリントン・トランジスタにも適用
可能である。The present invention is not limited to the semiconductor device of the above embodiment, and various modifications and applications are possible. For example, in the embodiment, an NPN Darlington transistor has been described, but the present invention is also applicable to a PNP Darlington transistor.
発明の効果
本発明によれば、オーディオ用ダーリントン・トランジ
スタの前段トランジスタの蓄積時間が短かくなり、これ
により実動作のクロスオーバ時に発生する縦電流を少な
くでき、トランジスタの発熱を押えるとともに、破壊耐
量の向上が可能となる。Effects of the Invention According to the present invention, the accumulation time of the preceding stage transistor of the Darlington transistor for audio is shortened, thereby reducing the longitudinal current generated during crossover during actual operation, suppressing the heat generation of the transistor, and increasing the breakdown resistance. It is possible to improve the
第１図は本発明の一実施例半導体装置の断面図、第２図
は実動作のクロスオーバ時における縦電流波形を示す波
形図である。
１・・・・・・Ｎ型コレクタ領域、２・・・・・・Ｐｉ
ベース領域、３・・・・・・Ｎ型エミッタ領域、４・・
・・・・Ｎ型分離エミッタ領域、５・・・・・・Ｎ型分
離エミッタ領域、６・・・・・・エミッタ電極、７・・
・・・・ベース電極、８・・・・・・コレクタ電極、９
・・・・・・内部電極、１０・・・・・・絶縁物。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名花
１ 因
４．、ｆ−＃型・介舟良１４・り禰８ゝ７
−−− べ一人４１＾
７Ｘ２図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing longitudinal current waveforms at crossover in actual operation. 1...N type collector region, 2...Pi
Base region, 3...N-type emitter region, 4...
...N-type separated emitter region, 5...N-type separated emitter region, 6...Emitter electrode, 7...
...Base electrode, 8...Collector electrode, 9
...Internal electrode, 10...Insulator. Name of agent: Patent attorney Toshio Nakao and one other person
1 cause
4. , f-# type, Keifune 14, Rine 8ゝ7
--- One person 41^ 7X2 diagram
Claims (1)
トランジスタに、そのエミッタ領域を囲んで、同エミッ
タ領域と同導電型の分離領域を有し、この分離領域を同
一トランジスタのベース電極に結線した半導体装置。A semiconductor device in which a front-stage transistor of a plurality of Darlington-coupled transistors has an isolation region surrounding its emitter region and having the same conductivity type as the emitter region, and this isolation region is connected to the base electrode of the same transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034659A JPH0714003B2 (en) | 1986-02-18 | 1986-02-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034659A JPH0714003B2 (en) | 1986-02-18 | 1986-02-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62190861A true JPS62190861A (en) | 1987-08-21 |
| JPH0714003B2 JPH0714003B2 (en) | 1995-02-15 |
Family
ID=12420567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61034659A Expired - Lifetime JPH0714003B2 (en) | 1986-02-18 | 1986-02-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714003B2 (en) |
-
1986
- 1986-02-18 JP JP61034659A patent/JPH0714003B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0714003B2 (en) | 1995-02-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |