JPS62202623A - ビツト速度調正の方法と装置 - Google Patents

ビツト速度調正の方法と装置

Info

Publication number: JPS62202623A
Authority: JP; Japan
Prior art keywords: adjustment; circuit; bit rate; buffer; pll
Prior art date: 1985-04-01
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Pending

Application number

JP61075368A

Other languages

English (en)

Japanese (ja)

Inventor

リー−グアング　ゼング

チユング−シ　フエング

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

KIANGU FUA UNIV

Original Assignee

KIANGU FUA UNIV

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-04-01

Filing date

1986-04-01

Publication date

1987-09-07

1986-04-01 Application filed by KIANGU FUA UNIV filed Critical KIANGU FUA UNIV

1987-09-07 Publication of JPS62202623A publication Critical patent/JPS62202623A/ja

Status Pending legal-status Critical Current

Links

230000033228 biological regulation Effects 0.000 title claims description 26
238000000034 method Methods 0.000 title claims description 12
238000011084 recovery Methods 0.000 claims description 6
238000012546 transfer Methods 0.000 claims description 4
230000002596 correlated effect Effects 0.000 claims description 3
230000001629 suppression Effects 0.000 claims description 2
230000008569 process Effects 0.000 description 9
230000005540 biological transmission Effects 0.000 description 7
230000001419 dependent effect Effects 0.000 description 7
238000001228 spectrum Methods 0.000 description 5
238000004891 communication Methods 0.000 description 4
238000001514 detection method Methods 0.000 description 4
238000012856 packing Methods 0.000 description 3
238000010586 diagram Methods 0.000 description 2
230000001105 regulatory effect Effects 0.000 description 2
230000003595 spectral effect Effects 0.000 description 2
230000001360 synchronised effect Effects 0.000 description 2
241000219112 Cucumis Species 0.000 description 1
235000015510 Cucumis melo subsp melo Nutrition 0.000 description 1
241000234295 Musa Species 0.000 description 1
FJJCIZWZNKZHII-UHFFFAOYSA-N [4,6-bis(cyanoamino)-1,3,5-triazin-2-yl]cyanamide Chemical compound N#CNC1=NC(NC#N)=NC(NC#N)=N1 FJJCIZWZNKZHII-UHFFFAOYSA-N 0.000 description 1
239000003990 capacitor Substances 0.000 description 1
238000006243 chemical reaction Methods 0.000 description 1
238000011181 container closure integrity test Methods 0.000 description 1
238000012937 correction Methods 0.000 description 1
238000011161 development Methods 0.000 description 1
230000000694 effects Effects 0.000 description 1
230000006870 function Effects 0.000 description 1
239000013307 optical fiber Substances 0.000 description 1
230000004044 response Effects 0.000 description 1
238000010183 spectrum analysis Methods 0.000 description 1
230000009466 transformation Effects 0.000 description 1

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/073—Bit stuffing, e.g. PDH

Landscapes

Engineering & Computer Science (AREA)
Computer Networks & Wireless Communication (AREA)
Signal Processing (AREA)
Synchronisation In Digital Transmission Systems (AREA)
Time-Division Multiplex Systems (AREA)

JP61075368A 1985-04-01 1986-04-01 ビツト速度調正の方法と装置 Pending JPS62202623A (ja)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
CN85100049		1985-04-01
CN85100049A CN85100049B (zh)	1985-04-01	1985-04-01	模型法码速调整方法及调整装置

Publications (1)

Publication Number	Publication Date
JPS62202623A true JPS62202623A (ja)	1987-09-07

Family

ID=4790845

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP61075368A Pending JPS62202623A (ja)	1985-04-01	1986-04-01	ビツト速度調正の方法と装置

Country Status (3)

Country	Link
EP (1)	EP0197492A3 (fr)
JP (1)	JPS62202623A (fr)
CN (1)	CN85100049B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4764941A (en) *	1987-05-22	1988-08-16	American Telephone And Telegraph Company, At&T Bell Laboratories	Digital frame synchronizer
SE466474B (sv) *	1990-07-10	1992-02-17	Ericsson Telefon Ab L M	Faslaasningskrets foer jitterreducering i digitalt multiplexsystem
DE4101270A1 (de) *	1991-01-17	1992-07-23	Siemens Ag	Verfahren zur uebertragung von digitalsignalen
FI95636C (fi) *	1992-02-14	1996-02-26	Nokia Telecommunications Oy	Desynkronisaattori ja menetelmä osoitinvärinän vaimentamiseksi desynkronisaattorissa
CN1045855C (zh) *	1992-10-15	1999-10-20	清华大学	数字式正/零/负码速调整方法和装置
US8297742B2 (en)	2010-03-19	2012-10-30	Fujifilm Corporation	Bonded circuits and seals in a printing device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3830981A (en) *	1973-04-02	1974-08-20	Bell Northern Research Ltd	Pulse stuffing control circuit for reducing jitter in tdm system

1985
- 1985-04-01 CN CN85100049A patent/CN85100049B/zh not_active Expired
1986
- 1986-04-01 EP EP86104448A patent/EP0197492A3/fr not_active Withdrawn
- 1986-04-01 JP JP61075368A patent/JPS62202623A/ja active Pending

Also Published As

Publication number	Publication date
CN85100049A (zh)	1986-08-27
CN85100049B (zh)	1987-11-25
EP0197492A3 (fr)	1988-01-07
EP0197492A2 (fr)	1986-10-15

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