JPS6223473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to junction field effect transistors, and more particularly to junction field effect transistors having multiple channels.

Junction field effect transistor (hereinafter referred to as J-FET)
The mutual conductance g _np in the case (abbreviated as ) is expressed as follows.

g _np ≒2a・e・μn・Nc・n・Z/l ...(1) However, 2a is the channel thickness, e is the electron charge,
μn is the mobility, Nc is the impurity concentration in the channel region, l is the gate length, Z is the gate width per unit number, and n is the number of gates.

In the conventional J-FET, in order to increase the mutual conductance, 2a, Nc
It was also necessary to increase the n·Z/l ratio.

However, channel thickness 2a and threshold voltage V
There is a relationship between _T as shown below.

2a≒(8ε _p ε _s ·V _T /lNc) – (2) where ε _p is the vacuum dielectric constant, and ε _s is the relative permittivity of the material forming the channel. Therefore, from equation (2), if the channel thickness 2a is increased, the threshold voltage V _T
This is not desirable in terms of the circuit, since a correspondingly large voltage is required to operate the J-FET. Next, when Nc is increased, the impurity concentration in the drain region and the source region is also the same as Nc, so the reverse breakdown voltage decreases. Furthermore, n・Z/l
In order to increase the ratio, it was necessary to increase n and Z, since l must be at most about 2 μm to be reproduced with good yield by photolithography in the manufacturing process.

Therefore, in order to actually increase the mutual conductance g _np of the conventional J-FET, due to the above-mentioned constraints, it was necessary to increase n and Z, have a large number of channels, and make the element pattern large. .

FIG. 1 is a plan view (a) and a cross-sectional view (b) taken along the line A-A' of a conventional J-FET. In the figure, 10 is a semiconductor substrate, 20 is an epitaxial layer serving as a channel region, 30 is a substrate extraction region, 40 is a gate region, 50 is a drain region, and 60 is a source region. In figure a, in a normal J-FET, l=2 μm, n=several lines to several hundred lines, and Z=several tens to several thousand μm.

In the conventional J-FET, n and Z had to be increased in order to increase the mutual conductance g _np without reducing V _T and reverse withstand voltage. However, as n and Z become larger, the element pattern also becomes larger, so when either n or Z is determined, the other is also limited in order to suppress the dimensional accuracy of photolithography within the chip. Furthermore, once n and Z are determined, the gate diffusion resistance R _G can be expressed as shown in the following equation.

R _G ≒ρ _s・1/n・Z/l (3) where ρ _s is the sheet resistance of the gate region. From equation (3), it can be seen that as Z increases, R _G also increases. For example, in Figure 1a, ρ _s = 10
When Ω/mouth, n=2, Z=500 μm, and l=2 μm, R _G ≒1250Ω. This R _G will contribute to the noise source resistance. FIG. 2 is a diagram showing the correlation between noise voltage en and frequency in J-FET. In the figure,
At frequencies below 10 Hz, flicker noise (also referred to as 1/noise) is dominant, and at frequencies above that, thermal noise is dominant. This thermal noise voltage e _o is expressed by the following equation.

e _o √4( _G +1 _np ) ...(4) However, K is Boltzmann's constant and T is the absolute temperature.

Therefore, the conventional J-FET has the disadvantage that increasing mutual conductance increases thermal noise voltage.

An object of the present invention is to increase mutual conductance without reducing cost, threshold voltage V _T and reverse breakdown voltage, and to reduce gate diffusion resistance R _G without reducing thermal noise.

FIG. 3 is a plan view (a) and a cross-sectional view (b) along the line A-A', showing an embodiment of the J-FET of the present invention. Fourth
The figures are a plan view (a) and a sectional view (b) in the direction of X-X' showing another embodiment of the J-FET of the present invention. In the figure, for example, in the case of an N-channel J-FET, 1 is a P-type semiconductor substrate, 2 is an N-type epitaxial layer, and 3 is a P-type semiconductor substrate.
4 is a P ⁺ type substrate extraction region, 4 is a P ⁺ type gate region, 5 is an N ⁺ type drain region, and 6 is an N ⁺ type source region. From Figure 3a and b, by short-circuiting the region where the vertical gate region and the horizontal gate region intersect to the semiconductor substrate at the same time when forming the substrate extraction region, the gate width that contributes to the noise source resistance can be reduced by separating the epitaxial layer. This is the distance from the substrate take-out area at the outer periphery to the area where the gate areas intersect. Therefore, if this distance is set to, for example, Z=2Z', the gate diffusion resistance R _G becomes R _G ≒ρ _s・1/n・Z′/l ...(5), which is 1/1 of the conventional value. It becomes 2. Similarly, (4) above
From the relationship in the equation, the noise voltage e _o will also be reduced. In addition, in the manufacturing process, if impurity diffusion is performed at the same time as forming the substrate extraction region, the gates and the gate substrate will be shorted, and no special manufacturing process is required, so the conventional manufacturing process can be used as is. There is no reduction in yield. Furthermore, it goes without saying that a P channel J-FET can also be manufactured.

[Brief explanation of the drawing]

Figures 1a and b are a plan view and a cross-sectional view in the A-A' direction of a conventional J-FET, Figure 2 is a noise voltage vs. frequency correlation diagram, and Figures 3a and b are the J-FET of the present invention.
A plan view and a sectional view in the A-A′ direction of the FET, and FIGS. 4a and 4b are a plan view and an X-
It is a sectional view in the X' direction. In FIGS. 1a and 1b, 10 is a semiconductor substrate, 2
0 is an epitaxial layer, 30 is a substrate extraction region, 40 is a gate region, 50 is a drain region, 6
0 is the source area. Figure 3 a, b and 4
In figures a and b, 1 is a semiconductor substrate, 2 is an epitaxial layer, 3 is a substrate extraction region, 4 is a gate region, 5 is a drain region, and 6 is a source region.

Claims (1)

[Claims] 1. A semiconductor layer of an opposite conductivity type is formed on a semiconductor substrate of one conductivity type, a semiconductor region of the one conductivity type is formed that reaches the semiconductor substrate and surrounds the semiconductor layer, and a semiconductor layer of the one conductivity type is formed in the semiconductor layer. A gate region is provided in contact with the semiconductor region in a mesh or lattice shape, source regions and drain regions are provided alternately in parts of the semiconductor layer divided by the gate region, and an insulating film covering the gate region. In a junction field effect transistor in which the source regions and the drain regions are electrically connected to each other by metal electrodes formed thereon,
A junction field effect transistor characterized in that at least one of the crossing portions based on the mesh or lattice shape of the gate region is continuous with the semiconductor substrate.