JPS6224331A - Device test control system - Google Patents

Abstract

PURPOSE:To facilitate the easy continuous and repetitive actions and to improve device test efficiency by accepting no processing request from another device while a test mode is designated and processing repetitively and successively the requests held by a stack memory. CONSTITUTION:A command control part 22 reads an unprocessed request out of a stack memory 10 and processes it. When the part 22 receives the ON signal of a test display latch 20, the part 22 decides unconditionally that the memory 10 always has a processing request for unprocessed request and reads a processing request out of an area indicated by a reading address register 16 of the memory 10 to process it. Then the register 16 is shifted to the next address. Thus the processing requests are processed continuously as long as a test mode lasts. When this processing is carried out up to the highest address area of the memory 10, the register 16 indicates an address '0' again. Thus the request processed previously is read out and processed repetitively.

Description

[Detailed Description of the Invention] [Summary] This is a control method for testing equipment in computer systems, etc. In a device that stores processing requests in a stack memory and processes them sequentially, if test mode is specified, it stops accepting processing requests and stores the processing requests held in the stack.
Process iteratively and sequentially. With this configuration, it is possible to economically realize a mechanism for testing the unit operation of the device.

[Industrial application field]

The present invention relates to a control method for testing devices in computer systems and the like.

2. Description of the Related Art Devices constituting a computer system, such as a storage control device, often adopt a method of processing requests by serializing them in order to efficiently process processing requests generated from a plurality of other devices.

Furthermore, when testing a device, it is often required to repeat a series of operations continuously and observe the state during that period.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram showing an example of the configuration of a computer system.

In the figure, 1 is a storage device, and a storage control device 2 is
Access requests to the storage device 1 from other devices, such as processing devices 3 to 5, are received via the lotus 6, and the storage device 1
control. Further, one of the processing devices, for example, the processing device 5, may be a so-called service processor, which is connected to each device of the system and processes monitoring and testing of each device, as is well known.

FIG. 3 is a block diagram showing an example of the configuration of the storage control device 2. As shown in FIG.

The stack memory 10 is a memory device having a capacity to store a required number of control information and data transferred from other devices as processing requests.

Processing requests are transmitted from the originating processing devices 3 to 5 via the bus 6.
Received by the input register 11, the command reception unit 12
As long as there is free space in the stack memory 10, processing requests are accepted, and processing request information in the input register 11 is stored in the area pointed to by the write address register 13 on the stack memory 10.

Thereafter, the address in the write address register 13 is updated by the address increment circuit 14 to point to the next area address. Note that when the address exceeds the capacity of the stack memory 10, the address increment circuit 14 returns the address value to 0 so that the stack memory 10 can be used repeatedly.

When there is an unprocessed processing request in the stack memory 10, the command control unit 15 reads out a set of processing request information from the area pointed to by the read address register 16 on the stack memory 10, passes it to the access control unit 18, and stores it. bag ff1
Perform the requested access to l.

Thereafter, the address in the read address register 16 is updated by the address increment circuit 17 to point to the next area address. Similarly to the address increment circuit 14, the address increment circuit 17 returns the address value to 0 when it exceeds a predetermined maximum value.

When testing the operation of the storage control device 2 having such a configuration, or testing the storage device 1 via the storage control device 2, a sequence of processing requests for executing appropriate operations is repeatedly and continuously performed. It is often necessary to perform processing and observe the status of required parts within the apparatus during the process.

Conventionally, even in such cases, a method has been adopted in which a processing request is generated from the processing device 5, which is a service processor, and sent to the storage control device 2. This method is not easy to operate, and as a result, the processing request cannot be processed a sufficient number of times. There was also a problem in that it was difficult to obtain continuous repetitive motion.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of a storage control device that replaces the storage control device 2, in which 20 is a test display latch that displays the test mode, 21 is a command reception section, and 22 is a command control section.

[For production]

It is assumed that the test display latch 20 is set by a service processor, for example, and indicates a test mode when it is on, and indicates a normal mode in which a test is not in progress when it is off.

While receiving the test display launch 200 ON signal, the command reception unit 21 stops accepting processing requests from the bus 6.

When the command control unit 22 receives the ON signal of the test display lunch 20, it sequentially processes the processing requests stored in the stack memory 10, assuming that there are always unprocessed processing requests in the stack memory 10.

Therefore, in the normal mode, after inputting a required number of processing requests via the bus 6 and stacking them in the stack memory 10, when the test display latch 20 is set to enter the test mode, the command control unit 22 inputs the required number of processing requests to the stack memory 10. Since a certain processing request is processed repeatedly while the test mode continues,
Continuous repeated processing is easily realized.

〔Example〕

In FIG. 1, in the normal mode in which the test display latch 20 is off, the command reception section 21 and the command control section 22 operate in the same manner as the command reception section 12 and the command control section 15 in the conventional configuration. 21 stores the processing request information in the area pointed to by the write address register 13 of the stack memory 10 and advances the write address register 13 to the next address, and the command control unit 22 stores the processing request information in the area pointed to by the read address register 16 of the stack memory 10. After reading and processing the processing request information, the read address register 16 is advanced to the next address.

The test display latch 20 is sent from the processing device 5, which is a service processor, for example, and indicates a test mode when it is on.

While receiving the ON signal from the test display latch 20, the command reception unit 21 stops accepting processing requests from the bus 6.
Save the memory contents of stack memo January 0.

In the normal mode, the command control unit 22 releases an unprocessed request from the stack memory only when it detects that there is an unprocessed request by comparing the addresses of the write address register 13 and the read address register 16. Read one and process it.

However, upon receiving the ON signal from the test display latch 20, the command control unit 22 unconditionally selects the stack memo 1.110.
Assuming that there is always an unprocessed processing request in the stack memory 10, the processing request is read from the area pointed to by the read address register 16 in the stack memory 10, processed, and the read address register is advanced to the next address.

In this way, as long as the test mode continues, the command control unit 22 processes the processing requests in the stack memory 10 one after another, and when the highest address area of the stack memory 10 is processed, the read address register 16 returns to the 0 address. Therefore, previously processed processing requests are repeatedly read and processed.

By resetting the test display latch 20, the normal mode is returned to and the above-described repetitive processing operation is completed.

Therefore, in the normal mode, if the required number of processing requests are manually input via the bus 6 and stacked in the stack memory 10, and then the test display latch 20 is set to enter the test mode, the processing request queue will be A continuous repeat process is executed.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to easily execute continuous repeated processing operations for testing equipment such as computer systems, and therefore it is a significant industry that improves the efficiency of equipment testing. It has a positive effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a computer system, and FIG. 3 is a block diagram of a conventional configuration. In the figure, (2) is a storage device, 2 is a storage control device, 3 to 5 are processing devices, 6 is a bus, 10 is a stack memory, 11 is an input register, 12.
21 is a command reception section, 13 is a write address register, 14.17 is an address increment circuit, 15.22 is a command control section, 16 is a read address register, 18 is an access control section, 20 is a test display latch Embodiment of the present invention IM block diagram Figure 1 Block diagram of a configuration example of a computer system Conventional -IRJ example block diagram Figure 3

Claims (1)

[Claims] In a device that accumulates processing requests from other devices in a stack memory (10) and sequentially processes the processing requests held in the stack memory (10), a test mode (20) is specified. During this period, processing requests from the other devices are not accepted (21), and the processing requests held in the stack memory are repeatedly processed in sequence (
22) A device test control method characterized by the following.