JPS6225575A - Encoding system for gradation facsimile picture signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a facsimile signal encoding system that allows the receiving side to freely select the quality of reproduced images, and particularly relates to a facsimile signal encoding system that allows a receiver to freely select the quality of a reproduced image. The present invention relates to a facsimile image signal encoding method useful for digital image communication and image database searches.

(Prior Art and its Problems) Conventional facsimile communication is paper-to-paper communication, and is a patented feature that obtains hard copies.

However, although there is a tendency for demands regarding image processing to become more diverse in the future, the current state of the art is that the conventional technology does not have a function that can sufficiently meet this demand.

With the diversification of facsimile communications, it is conceivable in the future that facsimile terminals will be used in combination with display devices to perform conversational image communication, image database searches, and the like. In such conversational image communication, in order to achieve smooth conversation, graphical information with a large amount of information is processed using the conventional image reproduction encoding method, that is, a complete image is sequentially reproduced from the top to the bottom of the image along the scanning line. I'm not going to play it (
It is more effective to use a sequential reproduction encoding method that displays a rough overall image on the display as early as possible and then gradually improves the image quality.

With the sequential reproduction encoding method, the recipient can determine whether the information is what he or she wants once a rough image is obtained, so if it is not needed, transmission can be stopped, eliminating unnecessary information transmission. I can do things. On the other hand, if the information is what you want, you can improve the image quality until you are satisfied, and if necessary, you can take a hard copy of the image at that point. In this way, the sequential reproduction encoding method allows for image selection, rapid search, and reduction in communication costs, and is an encoding method suitable for conversational image communication. Particularly, since gradation images have a large amount of information, the sequential reproduction encoding method is effective.

There are two factors that determine the image quality of a gradation image: resolution and the number of gradations. Therefore, as methods for gradually improving image quality using the sequential reproduction encoding method, there are two methods: one is to gradually improve the resolution, and the other is to gradually increase the number of gradations. Conventional sequential reproduction encoding methods for gradation images are either a method of gradually increasing only the gradations, a method of gradually increasing only the resolution, or a method of simultaneously increasing the number of gradations and resolution according to a predetermined algorithm. However, there is no sequential reproduction encoding method that can independently improve the number of gradations and resolution.

In order to eliminate these drawbacks of the prior art, the inventor of the present application proposed Japanese Patent Application No. 60-41084 entitled "Coding System for Gradation Facsimile Image Signal". However, it cannot be said that the method of this prior application makes sufficient use of the correlation between each corresponding pixel between image planes or its surrounding pixels.

(Objective of the Invention) In order to further improve the prior art, the present invention provides a sequential reproduction encoding method for gradation images that can independently improve the number of gradation levels and resolution.

(Structure and operation of the invention) The present invention will be described in detail below with reference to the drawings.

The original image to be encoded here is a multivalued image in which each pixel is expressed by N bits and has 2N gradations, but in the following explanation, the case where the value of N is 4 will be described.

First, one screen image is decomposed into four binary images (planes) using the BitBrain method, as shown in FIG.

The value of each bit plane is O(
white pixel) and l (black pixel)'.

Figure 2 shows the gradation value of the original pixel expressed as a pure binary signal.For example, if the gradation is 8, the pure binary signal is "01".
11", so bi-nodoplanes 1.2 and 3.4 are assigned in order starting from the MSB, and are "O" and "1" respectively.
1ftl+, becomes "1".

On the receiving side, if the information of plane 1 is first received, a binary image can be reproduced. In other words, the signal "O" may be displayed in correspondence with a white pixel, and the signal "1" may be displayed in correspondence with a black pixel. Next, plane 1 receives information from plane 2, which has already been received.
By combining the information, it is possible to reproduce a four-tone image. Similarly, by receiving the information on pull lane 3 and combining the already received information on planes 1 and 2, it is possible to reproduce an image with eight gradations. Furthermore, by receiving the information on plane 4 and combining the information on planes 1, 2, and 3 that have already been received, a 166-gradation image can be reproduced. In this way, the number of gradations can be selected depending on which plane's information is to be received.

The binarized plane 1 is encoded using a sequential reproduction encoding method for binary images, which will be described later. Here, for the sake of explanation, the resolution of the original image is assumed to be 16 pixels/mW.

If encoding is performed using a binary image sequential reproduction encoding method, the image quality can be gradually improved by first receiving a rough image and then receiving additional information. For example, first, encoded information of an image with a resolution of 1 pixel/l, which is thinned out every 16 pixels vertically and horizontally from the original image, is received. Next, 1
receiving additional information for an image with a resolution of pixels/N1;
Obtain an image with a resolution of 2 pixels/dragon. Furthermore, 2 pixels/l
Receive additional encoding information for an image with a resolution of 4;
Obtain an image with a pixel/dragon resolution. Similarly, 8 pixels/
It is possible to sequentially obtain images of a 1m, 16 pixel/dragon.

In this way, if encoding is performed using the binary image sequential reproduction encoding method, the resolution of the image can be selected depending on which additional encoded information is to be received.

Regarding the number of gradations, it can be translated into 3j4 depending on which plane information is to be received, and regarding the image resolution, it can be selected depending on whether additional encoded information of the binary image sequential reproduction encoding method is also to be received. . In this way, the present method is a sequential reproduction encoding method for gradation images that can independently improve the number of gradation levels and resolution.

The resolution and gradation expression capabilities of the terminals that access the image database center are not necessarily of the same type. Therefore, even when sending the same image data, a high-resolution image may be sent to one terminal, and a high-gradation image may be sent to another terminal. In such a case, if conventional encoding methods are used, the original images are stored and encoded each time according to the capabilities of the receiving terminal, which requires a large amount of memory and requires complicated processing. However, if images are stored in a database using the present encoding method using the method described below, processing is simple and the memory capacity is small.

Table 1 shows the method for storing image encoded information. First, regarding plane l, encoded information of an image with a resolution of 1 pixel per crane, which is thinned out every 16 pixels vertically and horizontally from the original image, is accumulated. Next, additional encoding information necessary to improve the resolution of the image with a resolution of 1 pixel/am to 2 pixels/am is stored. Similarly, additional coding information necessary to improve image resolution to 4 pixels/fin, additional coding information necessary to improve image resolution to 8 pixels/fin, and image resolution to 16 pixels/fin. The additional encoding information necessary to improve the performance is sequentially accumulated. Similarly, as shown in Table 1, plane 2. 3. The encoding information is stored for 4.

For example, when displaying an image with a resolution of 8 pixels/Tsuru and 8 gradations on the receiving terminal, the encoded information 1°2.3,4,6
, 7, 8, 9, 11.12, 13.14 is sufficient. If the receiving terminal displays the received information each time, it is possible to realize a display method in which a rough overall image is displayed at an early point and the image quality is subsequently improved, as described above. The order in which the information is received is encoded information 1. 2.
3. 4. 6゜7, 8. 9.11.12.13
．． For example, the order of encoded information 1.14 is not limited to the order of encoded information 1. 6.
11. 2. 7.12. 3゜8, 13. 4. 9
．． It may be in the order of 14. In the former case, a high-resolution image is obtained at a relatively early point in time, and the gradation increases thereafter. On the other hand, in the latter case, an image with high gradation is obtained at a relatively early point in time, and the resolution increases thereafter.

Table 1 Next, an example of a circuit configuration for realizing the encoding method of the present invention is shown in FIG. In the explanation here, the number of gradations of the original image is assumed to be 166 gradations (4 bits).

FIG. 3 shows an example of an encoding circuit. 1゜2 is an input terminal, 11 is a bit conversion circuit, 13 is an address control circuit (
I), 14 are address control circuits (III, 21.22°, 23 and 24 are each one screen memory, 31 is an encoding order control unit, and 41 and 42 are sequential reproduction encoders (11
and a sequential reproduction encoder (■), 51 is an output terminal, 61.6
2.63° and 64 indicate gates, respectively. below,
The operation of the circuit shown in FIG. 3 will be explained in detail. The signal of the original image to be encoded is sequentially received pixel by pixel from the input terminal 1 in order from left to right and top to bottom starting from the upper left of the image, and is transferred to the bit conversion circuit 11. The bit conversion circuit 11 decomposes a pixel expressed in 4 bits into a 1-bit signal, and converts it into M
One-bit signals from SB to LSB are transferred to one-screen memories 21, 22, 23, and 24, respectively.

The address control circuit (1113) controls the signals transferred from the bit converting circuit 11 to each screen memory 21, 22, 23, 2.
Indicate which coordinates in 4 are to be stored. Each screen memory 21, 22, 23, 24 has an address control circuit fI1
According to the instruction No. 13, information for one screen is accumulated in the same order as the order in which signals are read out from the original image (starting from the upper left of the image, from left to right, and from top to bottom).

When the transfer of information to each screen memory 21, 22, 23, and 24 is completed, the address control circuit (1113) transfers a signal indicating the completion of transfer to the encoding order control unit 31.

When the encoding order control unit 31 receives the signal, it opens the gates 61 to 64 and selects the plane to be encoded according to the encoding order stored in advance, and also sends the address control circuit tll) 14 to the encoded pixel, see Instructs pixel selection. Address control circuit (II) 14 is each -
Sequentially encoded pixels and reference pixels are extracted from the screen memories 21 to 24 and transferred to one or both of a sequentially reproducing encoder (1141) and a sequentially reproducing encoder (11142) through each gate 61 to 64. The encoder 4L 42 encodes the encoded pixels coming through each gate under the control of the encoding order control unit 31.Sequential reproduction encoding circuit fl)
4L (The encoded information output from II 142 is sequentially output to the signal synthesis circuit 43.

The signal synthesis circuit 43 outputs the plane display code outputted from the encoding order control unit 31 to the output terminal 51, and uses this code to distinguish the encoding plane,
, the output signal of the sequential reproduction encoder [) 41 is
In the case of planes 2, 3.4, a sequential reproduction encoder (n
) 42 is selected and outputted to the output terminal 51 following the plain display code.

Further, the above-mentioned encoding order is stored in advance in a memory provided in the encoding order control section 31. Therefore, by changing the contents of this memory, the encoding order can be arbitrarily set. This modification of the memory contents can be done on the transmitting side or on the receiving side. The signal input terminal for this purpose is input terminal 2 in the figure.

Next, the encoding algorithm in the present invention will be explained. As described above, the present invention actively utilizes the correlation between planes, but for plane 1, which is encoded first, there is no plane to refer to. Therefore,
Encoding algorithms are roughly divided into two: an encoding algorithm that is applied only to plane 1, and an encoding algorithm that is applied to other planes 2.3.4. The sequential reproduction encoder (1) 41 in FIG. 3 is for plane 1, and the sequential reproduction encoder (11+42) is for other planes.

As mentioned above, the encoding algorithm of the sequential reproduction encoder (I114) is described in detail in the prior art (Japanese Patent Application No. 58-235023 and Japanese Patent Application No. 60-41084). This will be explained below using FIGS. 4 to 8. FIG. 4 shows nine lines of !!1 to I!m+ZAY extracted from a certain part of the pixel signal.

(i) In the present invention, first, △X=2n (n=1.2.3-) pixels on the scanning line facing the lateral force, and △Y in the vertical direction.
= 2fi (n= 1.2.3-) pixels marked with ◎ in the figure are extracted, and the pixels are connected without dividing each line to perform run-length encoding. In Figure 4, n=2,
That is, pixels are extracted every four pixels or every four lines.

(ii) Next, the pixels marked with X in the figure are encoded, and at this time, the pixels marked with ◎ are referred to.

In other words, as shown in Fig. 5, when encoding an x-marked pixel, reference is made to the four ◎-marked pixels that have already been encoded and are separated by △X/2 in the horizontal direction and △Y/2 in the vertical direction. . The four ◎ mark reference pixels take the following 5 states.

State 0: When all 4 pixels are signal pixels State 1: When only 1 pixel among 4 pixels is black pixel State 2
: When 2 pixels out of 4 pixels are black pixels State 3: When 3 pixels out of 4 pixels are black pixels State 4: When all 4 pixels are black pixels Among these, in state B2, 2 pixels are white pixels. Therefore, it is thought that it corresponds to the outline of a character or figure, and the image quality is greatly influenced by whether the pixel marked with an X located at the center is white or black. Therefore, if the x before printing in state 2 is encoded and transmitted prior to other pixels, the image quality on the receiving side can be dramatically improved. From this perspective,
In the present invention, state 2. Condition 3. Condition B1. It is decided that the state will be encoded in the order of 4° state BO.

In addition, if interpolation processing (a kind of prediction) is performed on the receiving side in states O and 4, there is an extremely high probability that the interpolation will be white in state 0 and black in state B4 before x printing. , the degree of contribution to the image quality on the receiving side is low, and in some cases it may be possible to omit encoding.

As described above, as shown in FIG.
, and the state vN (N=0°-, 5) is attached to this to call it mode 1-N.

(iii) Next, the pixels indicated by △ in FIG. 4 are encoded by referring to the pixels marked ◎ and X, which have already been encoded. In this case, as shown in FIG. 6, the position of the reference pixel is ΔX/2. △
It will be located above, below, left and right in front of the △ print, which is Y/2 away. This encoding mode will be referred to as mode 2. The possible states of the reference pixel are the same as the states O to 4 described above, and the coding order before Δ printing, which takes into account the state of the reference pixel, is also the same as described above. The encoding mode of each state will be expressed as mode 2-N (N=0.·-14).

(iv) Next, the pixels marked with a circle in FIG. 4 are encoded. If the reference pixel pattern in mode 1 at this time is extracted from the diagram, it becomes Figure 7 +al~(dl, and the reference pixel exists at a position △X/2°△Y/2 away from the front of the ○ print to be encoded. In other words, in the procedure for encoding the image before x printing, the reference pixel extraction distance can be reduced to 1/2.

(V) Finally, the blank pixels in FIG. 4 are encoded.

If the reference pixel pattern at this time is extracted from the figure, the 8th
Figures (a) to (d) are shown, and in mode 2 encoding mode,
The distance to the reference pixel is △ 1/ of the value before printing is encoded.
It is now 2.

As mentioned above, mode 1. Mode 2 encoding is performed as a series of steps, which is repeated while reducing the reference pixel extraction distance to 1/2, and when the extraction distance reaches 21, encoding of all pixels is completed.

In addition, in the example of Figure 4, △X and △Y are set to 22=4, but 2
In n, n can be arbitrarily selected. Also, it is not essential to set △X and △Y equally; when the extraction distance of the reference pixel becomes 2, the distance in that direction is fixed to 2, and the sign of mode 1 and mode 2 is fixed until the other becomes 2. All you have to do is to

The above encoding procedure can be summarized in more detail as follows.

Step l-1: △X, △Y by 2” (n = 1, 2.3
Determined by ゜4, -----------).

Step 1-2 When the coordinates of two pixels are P, P(X△X
+1. Y ・△Y+1) (X, Y=0. 1-・-
1) are concatenated from left to right of the screen and then from top to bottom without dividing each line, and run-length encoding is performed.

Step 1-3: Encode according to a series of encoding algorithms shown in steps 2-1 to 2-10 described below.

Step l-4: Set ΔX to ΔX/2, and set ΔY to ΔY/2.

Step 1-5: If △X and △Y are both 1 (2 at the end of step 1-3), encoding is complete; otherwise, proceed to step 1-3.

Procedures 2-1 to 2-10 are configured as follows.

Step 2-1 = Perform mode 1-2 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1-2 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one black pixel that virtually conforms to mode 1-2 exists at the beginning of the screen.

Step 2-2 = Perform mode 1-3 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1 to 3 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one black pixel that virtually conforms to modes 1-3 exists at the beginning of the screen.

Step 2-3: Perform mode 1-1 encoding. - Run-length encoding is performed by sequentially connecting all pixels in the screen that fit mode 1-1 without dividing them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 1-1 exists at the beginning of the screen.

Step 2-4: Perform mode 1-4 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1 to 4 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one black pixel that virtually conforms to modes 1-4 exists at the beginning of the screen.

Step 2-5 = Perform mode 1-0 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1-0 in the screen without separating them line by line. First JL
As a J1 condition, encoding is performed assuming that one white pixel virtually matching mode 1-0 exists at the beginning of the screen.

Step 2-6: Perform mode 2-2 encoding. - Run-length encoding is performed by sequentially connecting all pixels in the screen that conform to mode 2-2 without dividing them line by line. As an initial condition, encoding is performed on the assumption that one black pixel that virtually conforms to mode 2-2 exists at the beginning of the screen.

Step 2-7: Perform mode 2-3 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 2-3 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one black pixel that virtually conforms to mode 2-3 exists at the beginning of the screen.

Step 2-8: Perform mode 2-1 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit mode 2-1 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 2-1 exists at the beginning of the screen.

Step 2-9: Perform mode 2-4 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 2 to 4 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one black pixel that virtually conforms to modes 2-4 exists at the beginning of the screen.

Step 2-10: Perform mode 2-0 encoding. - Run-length encoding is performed by sequentially connecting all pixels in the screen that conform to mode 2-0 without dividing them line by line. As an initial condition, encoding is performed on the assumption that one white pixel virtually matching mode 2-0 exists at the beginning of the screen.

Next, an example of codes used in each encoding procedure will be shown. Table 2 shows the code assignment table used in step 1-2.

Table 2 In Table 2, M H (W) means a code for white run in the MH encoding method, and WYLE means a known WYLE code. Table 3 shows the MH(W) termination code.
Table 4 shows makeup codes. Also, in Table 5, W
Indicates YLE code.

Note that 1-2 in Table 2 is unique to the present invention, and when expressed generally as rN-2J, the run length is 1 to 1.
In the range of 2 to 1, an N-bit code is used, and the run is NN
-1+ If it is 1 or more, it is a code in which 2 bits (l bit is a flag bit) are added as necessary.
Examples are shown in Table 6.

Table 3 Table 4 Table 5 Table 6 For the codes used in steps 1-3, the codes are used according to the code assignment table in Table 7, for example. In the table, NON
This means that the white of the image signal is encoded as "O" and the black as rlJ, and the rest is the same as in Table 1.

Table 7 Next, the encoding algorithm of the sequential reproduction encoder TII) 42 will be explained in detail with reference to FIGS. 4 to 10.

The four pixels closest to the encoded pixel are selected from among the pixels that have already been encoded. Hereinafter, the four selected pixels will be referred to as reference pixels. Refer to these four reference pixels to encode the pixel located at their center.The four reference pixels are located at the vertices of the rectangle as shown in Figure 9. The state at the apex of the rhombus is called mode 2. As shown in Figures 9 and 10, the interval between reference pixels in the horizontal direction is described as △X, and the interval between reference pixels in the vertical direction is described as △Y. The first pixel in the direction is expressed as P(1,J).

Let the four reference pixels be gi (!-I+...-14). These four reference pixels have already finished encoding up to plane N, and from the pixel values of planes 1 to N, the values of each reference pixel are 0≦g, ≦21'I-1 (i = 1.- , 4).

Furthermore, the value of the encoded pixel is f. (0≦f0≦2”-1)
shall be. Regarding the encoded pixels, it is assumed that encoding up to plane N-1 has already been completed, and its value is g. (0≦g0≦
2n-'-1), go and f. The relationship is f0=g0×2+h0. However, h is 1 or 0.

Therefore, if we know the value h0 of the encoded pixel of plane N, then f
The value of o can be found.

When encoding the value of ho, gt(i=D,...-14
) is used for encoding.

Furthermore, we provide the following definitions.

min min (g; : i = 1.-, 4] ma
x=max(gi:i=1.-,4)le
The value of vel "E max - m1nh0 is converted to 11° according to the following conditions.

+10=mod(ho+1.2) if ave<go

However, mod (i-j) indicates the remainder when i is multiplied by j.

The converted Ho is run-length encoded according to the method described later.

Furthermore, it is divided into four states depending on the state of gi (+"' 0+-.-24).

State 3: If 1evel = 0, State 2: (
goX2≧maxLIgoX2+1≦m1n)n(l
evel = 0 ) case state u 1 : (goX 2 =ave) n 1(
If Ivel = 0), the state is 0: ]
In the case of 匈3, in the case of state 3, f0=ave
There is a very high probability that Also, g0×2≧m in state 2
In the case of ax, the probability that ho=1 is very high. Also, g in state 2. If ×2+1≦min, h,=0
There is a very high probability that Conversely, in the case of state 0, ho
It is difficult to predict the value of , and if the encoded pixels belonging to state o are encoded and transmitted before other pixels, the image quality on the receiving side can be rapidly improved. From this point of view, in the present invention, state O1 state 1. Condition 2. Encoding is performed in the order of state 3.

Moreover, in mode M (M=0.1), state N (N=0.
−.

3) will be simply referred to as mode MN.

The coding order of pixels will be explained using FIGS. 4 to 8. FIG. 4 shows 9 lines from a certain part of the pixel signal on plane N, 1. ~I! This is an extraction of m+Zm'l.

(i) First, in the horizontal direction (on the scanning line) △X=2n (n=1
．． 2.3. ---) pixels, vertically △Y=2n(n=1
゜2, 3. -) Extract the pixels marked with ◎ in the figure that are separated by pixels, connect them without dividing them line by line, and perform run-length encoding. In Fig. 4, every n-2, that is, every 4 pixels,
Pixels are extracted every four lines.

(ii) Next, the pixels marked with an X in the figure are encoded,
At this time, the values of the pixels marked with ◎ on planes 1 to N and the pixels marked with X on planes 1 to N-1, that is, the aforementioned go + g l + g 2 +
Refer to the value of g, 3+g4. At this time, 3 separations from state O are performed as described above.

First, encoded pixels indicated by X marks in the figure are scanned starting from the top of the screen from left to right and from top to bottom. In other words, first, the H
Concatenate the values of o in order without separating them line by line,
Perform run-length encoding. Using the same method, mode 1-1. Mode 1-2. In the order of modes 1 to 3, the Ho values of all pixels matching each mode are sequentially connected, and run-length encoding is performed.

(iii) Next, pixels on plane N marked with Δ in FIG. 4 are encoded. In this case, the pixels on planes I to N marked with ◎ and X that have already been encoded and
The values of the pixels on planes 1 to N-1 marked with Δ, that is, the values of go, g++ gz+ g:++g4 described above are referred to. In this case, the positions of the reference pixels g1 to g4 are as shown in FIG. 6, from the △ mark pixel to be encoded to △x/2. They are located above, below, left and right of the △ print pixel, which is △Y/2 apart, and match mode 2. The possible states of the encoded pixels are the same as states 0 to 4 described above, and the encoding order of the Δ-marked pixels in consideration of the state of the reference pixel is also the same as described above.

(iv) Next, the pixels marked with a circle in FIG. 4 are encoded. If the pattern of reference pixels in mode 1 at this time is extracted from the diagram, it will be shown in Figure 7 (al to (d)). It is 1/2 of that.

As mentioned above, mode 1. Mode 2 encoding is performed as a series of steps, which is repeated while reducing the reference pixel extraction distance to 1/2, and when the extraction distance reaches 2', the encoding of all pixels is completed.

The above encoding procedure according to the present invention can be summarized in more detail as follows.

Step 1-1: Define △X and △Y as 2n (n=1.2°3.4.---1---.).

Step 1-2 = When pixel coordinates are P, plane N
Above P(X△X+1.Y・△Y+1)(X.

Y=0.1-.-) are connected from left to right of the screen and then from top to bottom without dividing each line to perform run-length encoding.

Step 1-3: Encode according to a series of encoding algorithms shown in steps 2-1 to 2-10 described below.

Step 1-4: Set △X to △X/2, and set △Y to △Y72.

Step 1-5: If △X and △Y are both 1 (2 at the end of step 1-3), encoding is complete; otherwise, proceed to step 1-3.

Procedures 2-1 to 2-10 are configured as follows.

Step 2-1: Perform mode 1-0 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1-0 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one white pixel virtually compatible with mode 1-0 exists at the beginning of the screen.

Step 2-2 = Perform mode 1-1 encoding. - Run-length encoding is performed by sequentially connecting all pixels in the screen that fit mode 1-1 without dividing them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 1-1 exists at the beginning of the screen.

Step 2-3 = Perform mode 1-2 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1-2 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 1-2 exists at the beginning of the screen.

Step 2-4: Perform mode 1-3 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 1 to 3 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one white pixel virtually matching mode i-3 exists at the beginning of the screen.

Step 2-5: Perform mode 2-0 encoding. - Run-length encoding is performed by sequentially connecting all pixels in the screen that conform to mode 2-0 without dividing them line by line. As an initial condition, encoding is performed on the assumption that one white pixel virtually matching mode 2-0 exists at the beginning of the screen.

Step 2-6: Perform mode 2-1 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit mode 2-1 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 2-1 exists at the beginning of the screen.

Step 2-7: Perform mode 2-2 encoding. - Run-length encoding is performed by sequentially connecting all pixels in the screen that conform to mode 2-2 without dividing them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 2-2 exists at the beginning of the screen.

Step 2-8: Perform mode 2-3 encoding. - Run-length encoding is performed by sequentially connecting all pixels that fit modes 2-3 in the screen without separating them line by line. As an initial condition, encoding is performed on the assumption that one white pixel that virtually conforms to mode 2-3 exists at the beginning of the screen.

Hereinafter, the encoding order control unit 31 used in the present invention will be explained in detail using the drawings. FIG. 11 shows an example of a circuit of the encoding order control section 31. 81 is an encoding order control circuit, 82 is an encoding order table, 83 is an encoding mode control circuit A that controls encoding to one-screen memory, and similarly, 84.85° and 86 are one-screen memory B, respectively. , - Screen memory C2 shows an encoding mode control circuit that controls encoding of one screen memory D.

Encoding mode control circuits 83, 84, 85, and 86 respectively control ΔX and ΔY encoding modes for encoding of the corresponding one-screen memory.

By storing the information, it is possible to remember up to which stage the encoding has been completed. The encoding order table 82 stores the encoding order in advance. Examples are shown in Table 8. Note that the contents of the table 82 can be rewritten under control from the input terminal 2, as described above. The encoding order control circuit 81 controls each encoding mode control circuit 83, 84, 8 according to the order stored in the encoding order table 82.
5. Instruct encoding to 86. For example, assume that a table such as Table 8 is set in the encoding order table 82, and encoding up to encoding order 10 has already been completed.

The encoding order control circuit 81 reads the contents of the encoding order 11 from the encoding order table 82. The encoding order control circuit 81 sends ΔX=4°ΔY=4 to the encoding mode control circuit C85 in order to encode the plane C according to its contents.
．． Mode 1. Instructs encoding of BO to 3. The encoding mode control circuit C85 is the encoding order control circuit 81.
According to the instructions, △X, △Y and mode are instructed to the address control circuit (II) 14, and
．． 63 is opened to instruct the sequential reproduction encoder (II) 42 to select the state and the code table to be used, and also to provide information on the encoding plane to the signal synthesis circuit 43. When the encoding is finished, a completion signal is sent to the encoding order control circuit 81. The encoding order control circuit 81 reads the contents of the encoding order 12 from the encoding order table 82 in order to perform the next encoding. The above procedure is repeated to perform encoding.

All the contents of the encoding order table 82 are processed, and four single-screen memories 83, 84, . When all the contents of g5.86 have been encoded, all the encoding has been completed.

Tables 8, 9, and 12 show an example of a sequential regeneration encoder (Ill 42).121 to 125 are gates 61 and 62, respectively.
．． gz, gz, from the pixel values transferred from one-screen memory A21 to one-screen memory D24 via
The figure shows a pixel synthesis circuit that creates g:+, g4°go, and reference pixel memories 131 to 135 store those values. Further, 136 is a memory for storing encoded pixel values transferred via one of the gates 61 to 64, 141 and 142 are comparators, 143 is an adder, and 14
4 is a multiplier, 145 is a subtracter, 146 is a divider, 147
．． 148 is an adder, 151 is a state selection circuit, 161 is a run-length encoding circuit, 171.173.174 is a gate, 172.175 is an OR circuit, 176 is an N07 circuit,
Reference numeral 181 indicates a sign inverter that converts "0" to "1" and rlJ to rOJ.

The encoding operation will be described below with reference to the configuration example of the encoding order control section 31 shown in FIG. 11 and the configuration example of the sequential reproduction encoder (n) 42 shown in FIG. 12.

First, according to the contents of the encoding order table 82, the encoding order control circuit 81 selects a plane to be encoded and a state. Here, as an example, the process of encoding plane 3 will be explained, and the operation of the encoding circuit will be explained.

Encoding mode control circuit C that controls encoding of plane 3
85 has △X, △Y, mode, and status, respectively.
It is stored in the Y mesori, mode memory, and state memory. First, the initial values of ΔX and ΔY are set in the ΔX and ΔY memories, and "0" is set in the mode memory and state memory, respectively.

First, encoding in step 1-2 is performed as follows. The encoding mode control circuit C85 first outputs the plain display code to the signal synthesis circuit 43. An example of plain display codes is shown in Table 9. For example, when encoding plane 3, a code of "10" is output. Furthermore, the encoding mode control circuit C85 is connected to an address control circuit (III 14).
The pixels to be encoded in step 1-2 are read out from the screen memory and instructed to be sequentially transferred to the reproduction encoder (II) 42. At that time, only the gate 63 is turned into an oven.

The encoded pixels are sequentially read out from the memory C23 under the control of the address control circuit (■) 140 and transferred to the pixel distribution circuit 121. The pixel distribution circuit 121 performs step 1
-2 encoding is detected by the encoding mode control circuit C85.
The encoded pixels that are transferred are sequentially transferred to the encoded pixel memory 136. In this procedure, the contents of encoded pixel memory 136 are routed directly to run-length encoding circuit 161. The run length encoding circuit 161 is an encoding mode control circuit C85.
The code table is selected according to the instruction from the encoder control circuit C85, and the gate 17 is opened according to the instruction from the encoding control circuit C85.
The contents of the encoded pixel memory 136 transferred via the encoded pixel memory 136 are sequentially run-length encoded and output to the signal synthesis circuit 43.

When the address control circuit (n) 14 finishes reading out the pixels to be encoded in step 1-2 from the one-screen memory, it instructs the encoding mode control circuit C85 to terminate encoding.

Next, the encoding mode control circuit C85 sets the contents of the mode memory provided therein to "1" and the contents of the state memory to "0" as described above, and performs encoding in step 2-1. This encoding mode control circuit C85 transfers the contents rOJ of the state memory to the state selection circuit 151. Furthermore, the run-length encoding circuit 161 receives the encoding order control unit 31 from the encoding order control unit 31 such that the content of the mode memory is "1" and the content of the state memory is "0".
Furthermore △X.

Receive the contents of ΔY, and write the values of ΔX, ΔY and mode 1-
A code table suitable for the encoding is selected from 0.

The address control circuit +11114 receives the values of △X and △Y from the △X and △Y memories, and receives "1" from the mode memory, thereby simultaneously selecting a reference suitable for mode 1 from each of the screen memories A to D. Pixel values are sequentially extracted and transferred to each pixel synthesis circuit via each gate. In that case, game 1-
Only the pixels 61, 62, and 63 are opened, and only the contents of the one-screen memories A to C are transferred to the pixel distribution circuit 121.

The pixel distribution circuit 121 calculates gz(i
=1. -, 4) are calculated and written into each of the reference pixel memories A to D, and at the same time go and the encoded pixel h0 are written into the reference pixel memory 0135 and the encoded pixel memory 136, respectively.

The comparators (11141, ゛(11) 142 each compare the reference pixel values g stored in the four reference pixel memories A-D.
The maximum value max and minimum value min are determined from i (+-1, -, 4) and transferred to the state selection circuit 151. Also,
The subtracter 145 subtracts the min value transferred from the comparator (U) 142 from the n+axO value transferred from the comparator (I) 141 to obtain 1evel, and transfers the value to the state selection circuit 151. Further, the adder 143 calculates the sum &gi of the four reference pixel values gi, and transfers the result to the divider. The divider 146 divides the value transferred from the adder 143 by "4" and calculates the average value a of the four reference pixel values g□.
ve is determined and the value is transferred to the state selection circuit 151.

The multiplier 144 calculates a value rgoX2J that is twice the reference pixel g0 stored in the reference pixel memory 0135, and transfers the result to the state selection circuit 151. Also adder 14
7.148 adds rlJ rO, 5J to the value transferred from the multiplier 144, respectively, and calculates rgoX2+I
J I”goX 2 +0.5J is calculated and output to the state selection circuit 151. Therefore, the state selection circuit 151 receives rg.

X 2J rgoX 2 +0.5j rgoX
2 + 1 j ravelrlevelJ rI
The value of IIinJ rmaxJ will be transferred.

Using these values, the state selection circuit], 51 selects the aforementioned states -0, W, , W2 . Find out which state W belongs to. Further, the state selection circuit 151 selects ravel and [g0
Compare ×2 + 〇, 5J, encoded pixel memory 13
When inverting the encoded pixel value h0 transferred from 6, the gate 1-174 is opened and the sign inverter 18
1 performs its inversion and is transferred to gate 171.

The state selection circuit 151 receives the state value “0” from the encoding order control unit 31, and the state that is the same as that value, that is, W
. The gate 171 is opened only when the following conditions are met. At that time, the contents of encoded pixel memory 136 are transferred to run-length encoding circuit 161. The run-length encoding circuit 161 encodes the run-length encoding of the encoded pixel value using the predetermined code table using the method described above, and outputs it to the signal synthesis circuit 43. When the address control circuit (IT) 14 finishes reading out all the pixels to be encoded in modes 1 to 0 in the one-screen memory, it instructs the encoding mode control circuit C85 to terminate encoding. Next, the encoding mode control circuit C85 "engineers" the contents of the mode memory.

The contents of the state memory are set to "1", the same operation is performed, and the pixels are encoded in step 2-2.

Thereafter, encoding in steps 2-2 to 2-10 is performed in the same manner.

However, in each step, mode selection memory,
The contents of the state memory are as follows.

Step 2-3: Contents of mode selection memory "1" Contents of state memory "2" Step 2-4: Contents of mode selection memory "1" Contents of state memory "3" Step 2-5: Contents of mode selection memory "2" Contents of status memory "0" Step 2-6: Contents of mode selection memory "2" Contents of status memory "1" Step 2-7: Contents of mode selection memory "2" Contents of status memory "2" Step 2-8: Contents of the mode selection memory "2" Contents of the state memory "3" After completing such encoding, the encoding mode control circuit C
85 means that if the contents of △X and △Y in the △X and △Y memories are respectively "1", the contents of △ After changing to ΔY/2, the encoding from step 2-1 to step 2-10 is repeated. Furthermore, if the contents of HX and ΔY in the ΔX, ΔY mesori are both "1", the encoding ends.

The circuit operation described above is for encoding the entire contents of one screen memory. The encoding mode control circuit C85 performs step 1-22 step 2-1, step 2-21 step 2-10 order 2-41 step 2-51 step 2-10 order 2-72 step 2-82 step 2- Each time step 102-10 ends, it is determined whether the encoding has been completed up to the encoding stage instructed by the encoding order control circuit 81, and if it has not yet been completed, the encoding is further advanced. Furthermore, when the encoding up to the encoding stage instructed by the encoding order control circuit 81 is completed, the encoding mode control circuit C8
5 instructs the encoding order control circuit 81 to finish, and △X
, ΔY, mode, state, etc., and suspends operation until an encoding instruction is received from the encoding order control circuit 81.

FIG. 13 shows an example of a decoding circuit,
301 is an input terminal, 311 is a plane display code extraction circuit, 312 is a decoding plane determining unit, 321 is a sequential reproduction decoding circuit, 331.332.333.334.335.33
6°337, 338 are gate circuits, 341.342.3
43. 344 are one-screen memory A for storing binarized planes, -screen memory B, -screen memory C1, one-screen memory D, 351 and 353 are address control circuits (I) and (If), 352 is a bit synthesis circuit, 36
1 is a gradation image one-screen memory for storing gradation images;
371 indicates an output terminal.

As an initial state, "1" is stored in all the memories in the four single-screen memories 341 to 344, and "15" is stored in all the memories in the gradation image single-screen memory 361.

An encoded signal is received from an input terminal 301.

The plane display code extraction circuit 311 extracts the plane display code from the signal received from the input terminal 301, transfers the code to the decoding plane determination section 312, and sequentially transfers the other codes to the reproduction decoding circuit 321.

The sequential reproduction decoding circuit 321 decodes the encoded signal transferred from the plane display code extraction circuit 311 according to instructions from the decoding plane determining section 312. Further, the address control circuit (I) 353 reads reference pixel values from each of the screen memories A to D, and sequentially transfers them to the reproduction decoding circuit 321 via gates 335 to 338. The decoding plane determination unit 312 determines that the plane display code transferred from the plane display code extraction circuit 311 and the code transferred from the input terminal 301 after the plane display code from Table 10 are as follows.
By determining which plane it relates to and opening any of the gates 331 to 334 accordingly, the plane to be decoded is selected and the reproduction decoding circuit 321 is sequentially controlled. for example,
When receiving the plane display code "10" from the plane display code extraction circuit 311, the decoding plane determining unit 312 opens the gate 333 to decode the information of plane C, and sequentially reproduces the information of plane C so as to decode the information. Instructs the decoding circuit 321. The minimum unit of decoding is each procedure unit (procedure 1-2, procedure 2-11 procedure 2-2, -
----・2 Step 2-9 or Step 2-10) When the decoding of that unit is completed, the sequential reproduction decoding circuit 321 sends a signal to the decoding plane determination unit 312 to instruct the decoding end. Forward. When the decoding plane determination unit 312 receives the signal, it closes the open gate (any one of the gates 331 to 334) and further transfers the decoding end signal to the plane display code extraction circuit 311. Further, when the plane display code extraction circuit 311 receives a decoding end signal from the decoding plane determination unit 312,
The plane display code is extracted from the signal input from the input terminal 301, and the above procedure is repeated.

The sequential reproduction decoding circuit 321 transmits the decoded image information signal to one screen memory (single screen memory A) via an open gate (one of gates 331 to 334).
341 to one of the one-screen memories D344) and stored therein.

The address control circuit 351 includes four single-screen memories 341 to
344 and the same coordinates of the gradation image one screen memory.

The four single-screen memories 341 to 344 transfer the memory contents of the coordinates specified by the address control circuit to the bit synthesis circuit 35.
Transfer to 2. The bit synthesis circuit 352 uses the bit information transferred from the one-screen memories 341 to 344 to
Gradation image signals (4 bits) are synthesized according to the table and stored in the memory at the coordinates specified by the address control circuit 351. For example, when the signals transferred from the one-screen memories 341 to 344 are "1", "0", "1", and "0", respectively, the gradation image signal to be synthesized is "6".

After all the decoding by the sequential reproduction decoding circuit 321 is completed, the address control circuit 351 performs the above procedure for all coordinates sequentially from left to right and top to bottom, starting from the upper left corner pixel of one screen. . As a result, decoded gradation image information is obtained in the gradation image one-screen memory 361.

The decoding plane determination unit 312 will be explained in detail below using the drawings. FIG. 14 shows an example of a circuit of the decoding plane determining section 312, where 381 is a decoding plane determining circuit, and 382 is a decoding mode control circuit that controls decoding of the single screen memory A341. and
Similarly, 383, 384, and 385 are each one-screen memo I
JB342. One-screen memory C343 indicates a decoding mode control circuit that controls decoding of one-screen memory D344. Decoding mode control circuit 382.38
3, 384, and 385 store information such as ΔX, ΔY, mode, state, etc. regarding the decoding of the corresponding one-screen memory, thereby storing the stage at which the decoding has been completed.

As mentioned above, the decoding plane determination circuit 381 uses the plane display code transferred from the plane display code extraction circuit 311 to determine the code transferred from the input terminal 301 after the plane display code according to Table 10. By determining which plane (one screen memory) it relates to and opening any of the gates 331 to 334 accordingly, the plane to be decoded is selected, and the plane that is directly connected to the opened gate is selected. One screen memory (One screen memory 341 to 344
A signal instructing decoding is transferred to a decoding mode control circuit (any one of decoding mode control circuits 382 to 385) that performs control regarding decoding (any one of decoding mode control circuits 382 to 385). The decoding mode control circuit that receives the signal performs one procedure of decoding. After the decoding is finished, the decoding mode control circuit instructs the decoding plane determining circuit 381 to finish the decoding. After that, the decoding plane determination circuit 381
transfers a decoding completion signal to the plane display code extraction circuit 311.

FIG. 15 shows a configuration example of the sequential reproduction decoding circuit 321 used in the decoding circuit of FIG. 13.

231 is one screen memory A341 to one screen memory D344
From the pixel values transferred from g++, gz+ g:
+, gar g.

251 to 255 indicate memories for storing these values. In addition, 256 is a run-length decoder, 257 is a run-length decoder, and 257 is a run-length decoder that converts “0” to
” sign inverter, 261.262 is a comparator, 2
63 is an adder, 264 is a multiplier, 265 is a subtracter, 26
6 is a divider, 267 and 268 are adders, 271 is a state selection circuit, 224 is a FIFO buffer, 222° 223
is the decoded pixel address determination circuit, 244.245.246
゜247 is the gate, 248 is the NOT circuit, 249 is the OR
Shows the circuit.

The decoding plane determination circuit 381 selects a plane to be decoded according to the plane display code transferred from the plane display code extraction circuit 311. Here, as an example, the process of decoding plane 3 will be explained, and the operation of the decoding circuit will be explained.

Decoding mode control C3 that controls plane 3 decoding
84 has △X, △Y, mode, and status, respectively.
It is stored in Y memory, mode memory, and state memory. First, the initial value is △X.

The initial values of X and ΔY are set in the ΔY memory, and "0" is set in the mode memory and state memory, respectively.

First, decoding in step 1-2 is performed as follows. The values of ΔX and ΔY and the contents of the mode memory and state memory are respectively transferred to the run-length decoder 256, and a code table suitable for decoding in step 1-2 is set therefrom. Thereafter, the run-length decoder 256 sequentially receives the codes transferred from the plain display code extraction circuit 331 and performs run-length decoding. Further, the decoding mode control circuit C384 opens the gate 245.

The decoded signal is transferred via the gate 245 to the decoding side single element address determination circuit m223. The decoded pixel address determination circuit (I) 223 reads △X, △Y from the △X, △Y memory.
The contents of △Y are received, and all pixels CP (to NX X+1.M
X△Y+1), (N, M'=0,・1,2.−・
. - When the above-mentioned operation is completed for all the screens, a completion signal is sent from the decoding pixel address determination circuit (I) 223 to the decoding mode control circuit 384. At this point, step 1-
All pixels encoded with 2 are decoded. The decoding mode control circuit 384 includes a decoding pixel address determining circuit (1
Upon receiving a signal from 1223, gate 245 is closed.

At the same time, the decoding mode control circuit 384 instructs the decoding plane determining circuit 381 to terminate decoding.

Next, when the decoding mode control circuit 384 receives a decoding instruction from the decoding brachy determination circuit 381, the decoding mode control circuit 384 performs step 2.
-1 encoded pixels are decoded. The decoding mode control circuit 384 sets "1" in the mode memory and "2" in the state memory, and then sets ',, --)244.335
．． 336. Open ss□. , 7,7 Guyu decoder 256
receives the values of △X, △Y from the △X, △Y memory, and transfers the mode value (“1” when decoding the pixel encoded in step 2-1) from the mode memory to the state memory. The code table is determined by receiving the state value (“2j” when decoding the pixels encoded in step 2-1), and the decoding of the required run length is performed sequentially.Decoding The signal is sent to the FIFO buffer 22 via the gate 244.
Transfer to 4. The address control circuit (1) 353 is
, △Y memory, and ``1'' from the mode memory, 4 suitable for mode 1 (see Fig. 4) is selected from each screen memory 341 to 344. The pixel values of the two reference pixels are transferred to the pixel distribution circuit 231 sequentially (from the left to the right of the screen and from top to bottom) via gates 335 to 337. Pixel distribution circuit 231
Since it is informed from the information from the decoding mode control circuit C384 that this is decoding in step 2-1 of plane C, g+(i=1...-94) is calculated from the pixel values transferred. Each reference.

The reference comparators (11261, (II) 262 write the reference pixel values g stored in the four reference pixel memories A to D, respectively) and simultaneously write go to the reference pixel memories A to D.

Maximum value max and minimum value m from (i=1.-・,4)
in is determined and transferred to the state selection circuit 271. Further, the adder 263 calculates the sum of the four reference pixel values g, 8g.

and transfers the result to the divider 266. Divider 2
66 divides the value transferred from the adder 263 by "4" to obtain an average value raveJ, and transfers the value to the state selection circuit 271. Multiplier 264 calculates a value rgoX2J that is twice the reference pixel g0 stored in reference pixel memory o255, and outputs the result to state selection circuit 271. Adders 267 and 268 add rlJ ro and 5J to the values transferred from multiplier 264, respectively, and
goX 2 + I J rgoX 2 +0.5J
is determined and output to the state selection circuit 271. Therefore, the state selection circuit 271 has raveJ rlevelJ
rminJrmaxJ rgoX2J rgoX2
+IJ rgoX2+o, the value of 5J will be transferred. Using these values, the state selection circuit 271 determines to which state of the above-mentioned states -6, W, . In addition, the state B selection circuit 151 uses raveJ
and rgoX 2 +0.5J, and the inversion of the decoded pixel value H0 transferred from the FIFO buffer 224 (
If it is "0", it is changed to "1"; if it is "1", it is changed to "0"). When performing inversion, gate 247
is opened, and the sign inverter 257 performs its inversion. The state 6 selection circuit 271 is set to the state value “0” by the decoding mode control circuit 382, 383, 384° 385.
is received, and the gate 222 is opened only when the state is the same as that value, that is, the state of −0. At that time, the value of one pixel in the FIFO buffer 224 is
It is transferred via gate 222 to each screen memory. Since only the gate 333 is open at that time, its contents are transferred to the one-screen memory C343 and written to the address of the encoded pixel indicated by the address control circuit ([1351).

When the decoded pixel address determination circuit CI) 223 finishes reading out all the pixels to be encoded in modes 1 and 0 in the one-screen memory, it instructs the encoding mode control circuit C384 to terminate encoding. Next, the decoding mode control circuit C384 sets the content of the mode memory to "1" and the content of the state memory to "1".
Then, simultaneous operations are performed to perform pixel encoding in step 2-2.

Thereafter, the pixels encoded in steps 2-3 to 2-10 are similarly decoded. However, the contents of the mode memory and state memory in each case are as follows.

Decoding of pixels encoded in step 2-3: Contents of mode memory "1" Contents of state memory "2" Decoding of pixels encoded in step 2-4: Contents of mode memory rlJ Contents of state memory "3" Decoding of pixels encoded in step 2-5: Contents of mode memory "2" Contents of state memory "0" Decoding of pixels encoded in step 2-6: Contents of mode memory "2-" Contents of state memory "1" Decoding of pixels encoded in step 2-7: Contents of mode memory "2" Contents of state memory "2" Decoding of pixels encoded in step 2-8: Contents of mode memory "2" State memory Content “3” After completing the above decoding, the decoding mode control circuit 384
If the contents of △X and △Y in △X, △Y memory are not "1", then the contents of △X and △Y are transferred to X/2, △Y/ respectively. After changing to step 2, the decoding procedure of the pixel encoded in step 2-1 to step 2-
The decoding procedure for the encoded pixels in step 10 is repeated.

Further, if the contents of ΔX and ΔY in the ΔX and ΔY memories are both "1", the decoding is terminated.

The address control circuit (II) 351 sequentially reads the contents of each of the screen memories 341 to 344 from the upper left of the screen and transfers them to the bit synthesis circuit 352. The bit synthesis circuit 352 creates gradation values from these values and stores them sequentially from the upper left of the screen in the gradation image one-screen memory 361.

When the above operation is completed for the entire screen, a gradation image is output from the output terminal 371.

Although one embodiment of the present invention has been described above, the order of steps 2-1 to 2-10 in the present invention is not limited to the above-mentioned order.
The order of steps 2-6 to 2-10 can be changed.

Also, when encoding the corresponding pixels in Steps 1-2 and 2-1 to 2-10, any known encoding method can be used, regardless of the run-length encoding method.

Further, the address control circuit 351 does not necessarily need to perform the above procedure after all the decoding by the sequential reproduction decoding circuit 321 is completed, but starts the above procedure in the middle of decoding.
When the processing is completed for all coordinates on one screen, the above procedure may be repeated sequentially from the first pixel (the pixel at the top left of the screen) until the decoding is completed. the result,
For example, the contents of the gradation image one-screen memory 361 are always CR
If the image is displayed on a T-display, a rough image will be displayed at first, and the image quality will gradually improve as decoding progresses. Furthermore, in order to improve the quality of the image displayed on the receiving side as much as possible, it is also possible to perform interpolation processing on undecoded pixels. As the interpolation process, conventional techniques such as a method of representing the pixel using the nearest decoded pixel can be used.

In the above embodiment, the average value ave, the maximum value max, the minimum value min, and the difference value 1eνel between the maximum value and the minimum value of the four reference pixels are used. It was separated into four states using the value of . However, the separation of states is not necessarily limited to the above-mentioned method; for example, the following states may be considered.

(il Method of separating with difference value 1eνel 1evel
Separate states by O value. It is not necessary to set individual states for all values; they can also be grouped.

For example, state ffQ 1: Ievel=0 state 62:
1evel = 1 State 7G3: Ievel = 2 State 4: Ievel = 3 State a 5: Ievel = 4 State 6: 1evel = 5 (iil Method of separating by average value ave Separate states by average value. For all values It is not necessary to set individual states, and it is possible to group them. For example, state 1: (ave)≦6 state 2: (ave) -7 state 3: (ave) = 8 state 4: (ave) = 9 State 5: (ave) = 10 State 6: (avel≧II However, [] is a Gaussian symbol (ii) Method of separating by comparing go and ave For example, State 1: goX 2 +0.5<aνe State 2
: goX 2 +0.5=ave state 3 : g
oX2 +0.5>ave(iv) go and min,
For example, state 1: gox2≧max state a2: goX 2 + 1≦min state 3:
In addition to states B1 and B2, states can also be separated by combinations of these (i) to Gv).

(Effects of the Invention) As described in detail above, according to the present invention, a sequential reproduction encoding method with high encoding efficiency can be realized even for multi-tone images. In particular, by introducing the bitplane method,
Image quality can be selected from two aspects: resolution and number of gradations, and it becomes possible to transmit information with just the right amount depending on the resolution and gradation expression ability of the receiving terminal. This is particularly noticeable when the present invention is applied to an image database storage method that communicates with many types of terminals.
Communication costs can be significantly reduced.

Note that the effects of the present invention are compared with those of the prior art in terms of the number of bits required when encoding an actual image.

The images used are GIRL, which is included in the 5IDBA image database proposed by the University of Tokyo Institute of Industrial Science.
(256×256 pel) is requantized to 16 gradations. When this image is encoded using the conventional technique, the number of encoded points is 77,527.22 bits, and when encoded according to the present invention, it is 73,486.24 bits.

Therefore, the present invention aims to improve the coding rate by about 5.5% compared to the prior art.

[Brief explanation of drawings]

FIG. 1 is a schematic perspective view for explaining the decomposition of an image by the bit plane method used in the present invention, FIG. 2 is a diagram for explaining the relationship between each plane and gradation used in the present invention, Fig. 3 is a block diagram showing an embodiment of the present invention, Fig. 4, Fig. 5, Fig. 6 (a) (b), Fig. 7 (a)
(b) fc) (di, Fig. 8(a) (b) (
C) (d), FIGS. 9 and 10 are pixel arrangement pattern diagrams for explaining the principle of encoding used in the present invention, and FIG. 11 is a diagram of one of the encoding order control units used in the present invention.
FIG. 12 is a block diagram showing an example of a sequential reproduction encoder used in the present invention; FIG. 13 is a block diagram showing an example of a decoding circuit for encoded signals according to the present invention; FIG. 13 is a block diagram showing an example of a decoding plane determining section used in the circuit example of FIG. 13, and FIG. 15 is a block diagram showing an example of a sequential reproduction decoding circuit used in the circuit example of FIG. 13. 4th ward, 15th flash, 6th (aL'> (-b”) - 3rd
0 spear 70 spear 8 closed

Claims (1)

[Claims] 2^ A means for creating bit planes by decomposing a multi-gradation facsimile image signal expressed in n layers into n bit planes corresponding to n digits, and a means for creating bit planes from among the pixels constituting each bit plane. An initial encoding means that extracts pixels every △X pixels from each line and encodes these pixels, and the same position as the four pixels located at the vertices of the smallest rectangle among the encoded pixels. a mode 1 encoding means for encoding a pixel located at the center surrounded by the four reference pixels by referring to the pixels of each plane that have already been encoded; the initial encoding means; and the mode 1 encoding means; Among the pixels encoded by the encoding means 1, the pixel located at the center is determined by referring to the pixels of each plane that have already been encoded and are located at the same position as the four pixels located at the vertices of the smallest rhombus. and a mode 2 encoding means for encoding,
2^n(n
= integer) as the initial values of △X and △Y, initial encoding and mode 1 and mode 2 encoding are performed, and after this, △X and △
A method for encoding a gradation facsimile image signal, characterized in that the value of Y is divided into two and encoding in mode 1 and mode 2 is repeated.