JPS62257531A - Information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device using a microprogram control method, and is particularly applicable to a microprogram loading method.

[Background of the invention]

A microprogram-controlled information processing device is programmed with a microinstruction set that specifies the basic operations of the processing device, stores this in a control storage device, and sequentially reads and executes the microinstructions to control the operations of the processing device. Realize.

Conventionally, a control storage device configured with a fixed memory and a variable memory is disclosed in, for example, Japanese Patent Laid-Open No. 58-200346. However, since the data bit width per address of one element in the fixed memory where the initial program load program is stored is usually smaller than the bit width of the microinstruction word length, several fixed bit widths are required. J'e: By arranging them in parallel and reading out the contents of the same address of each fixed memory in parallel, bits corresponding to the bit width of the microinstruction are obtained. However, with this method, if the number of words specified by the fixed memory element is larger than the total number of microprograms to be stored, unused portions of the fixed memory will be wasted, and the microinstruction focus [I
There is a problem in that as J increases, the number of fixed memories used increases.

[Purpose of the invention]

An object of the present invention is to solve such conventional problems and provide an information processing device that can reduce the number of fixed memories used for storing microprograms by adding a small amount of hardware. In particular, this applies to the microprogram loading method.

[Summary of the invention]

fI is a microprogram control system in which the control storage unit is composed of a fixed memory and a variable memory! In the first report processing system, after the power is turned on, it is necessary to load the microprogram from the external storage medium to the variable memory by executing the microprogram loader stored in the fixed memory. Conventionally, a 48-bit wide microprogram loader as shown in FIG. 6 is mounted on six 8-bit x 4 K a fixed memory elements as shown in FIG. By executing the microprogram while reading it, the microprogram is loaded from the external storage medium into the variable memory. However, in many cases, it is not necessary to store the microprogram in the external storage unit storage medium (the variable memory has 8 pins), and for example, it is not necessary to store it in the fixed memory of 1111 I11. Note that it is possible to move from the fixed memory to the variable memory? jl Wl program load By providing a display means to distinguish whether a program is being loaded or a normal microprogram is being executed, by once loading the contents of the fixed memory into the variable memory and executing it, IJiI This device is characterized in that the number of fixed memories ν2 can be stored at any time.

[Practice of the invention 1] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of the present invention I! It is a schematic system construction diagram of an information processing device that explains A+. FIG. 2 is an operational flow from power-on to execution of micro N-minute set. FIG. 3 is an example of a microinstruction format. Figure 4 shows the conventional microprogram loading method. FIG. 5 is a microprogram loading method of the present invention in comparison with FIG. 4. FIG. 6 shows an example of the operation shown in FIG.
The control storage unit 108 is composed of a RAM, and when the power is turned on, a program for loading a microprogram stored in the ROM 101 or a program stored in the C8 is executed. An information processing device in which a microprogram is loaded into the control storage unit @108 will be described.

FIG. 2 shows an operation flow from power-on to execution of a microinstruction set. When power is turned on 201, the hardware performs cent operations 202 such as registers and flags. after that,? /J 191 Program load 203 is executed, and self a m 204 by the microprogram is executed. If the self-diagnosis song 204 is successfully completed, a microprogram is loaded 205 and a set of microinstructions specifying the basic operations of the processing device is executed 206. FIG. 3 shows a microinstruction format 301 used in Akira Hontsuko's embodiment, and the bit width per instruction is 148 bits. FIG. 4 shows a microprogram loading method according to the prior art. In order to store a microprogram for loading a microprogram, six data widths of 8 bits and a depth of 4 are written in word R.
A 48 btt width microinstruction format 301 is realized using OMs 401 to 406. However, since the program capacity for loading the microprogram only needs to be small, the lower address portions of each ROM 401 to 406 will be empty. FIG. 5 shows an embodiment of the present invention, and if the program for loading a microprogram can fit into 512 steps, the data width is 8 kl.
It can be stored in the imperial ROM 501111/j at depth 4. When the power is turned on, control,! ;Load sequentially from upper byte to lower byte in 512-byte block units to RAM group 108 that constitutes the I storage device ROM0 block → RAM o block ... ROM5 block →
RAM 5 blocked. This loading process is performed by dedicated hardware. A specific example is shown in FIG. In FIG. 6, the microprogram, counter 107 (
μPC (lattice) is 14 bits wide and can create 16 addresses. Mata, μP
The output of C107 is ROM5o1 and RAM608~6
It is connected to 13. In the embodiment of the present invention, the capacity of the control storage device 108 is 48 bits)
It is g. The operation will be explained step by step according to FIG.

(1) When the value of μP C107 is between 0000 and 01FF, the AND gate 605 outputs a logic signal level 1' and chips-enables the ROM 501. R.O.
M501 has 8 btt width data f, RAM 60
However, during this time, the output of the flip-flop 601, which is set to CPU reset 1, and the output of the decoder 607, which decodes bits 11 to 9 of the μPC 107, cause the RAM 608L to be supplied to the RAM 608L.

The output data of ROM 501 is stored in G from address 0 to address 512 of RAM 608.
This is taken in.

(11) The value of μP C107 is 0200~0! l
During FF, bits 12 to 9 of the RAM address are kept in a high impedance state by the dry state gate 621, so the output data of the ROM 501 is It fits into the address.

(fit) Similarly to (11) below, μPC10
If the value of 7 is between 0400 and o5FF, it is sent to RAM61o, and between 0600 and 07FF, it is sent to rtAM611, and 08
Between 00 and 09FF, to IIAM612, 0A00 to
During 0BFF, the output data of ROM 501 is taken from address 0 to address 512 of RAM613.0Qv) When the value of μPC1o7 is between 0C00 and 0FFF, the contents of ROM 5 (11) are output. Since none of the RAMs 608 to 61 are chip-selected by the output of the flip-flop 601 and the decoder 607, no data is taken into the RAM during this time and the μPC 107 is only updated.

(■) μP(:'107 value is 1000 to 3FF
During F, the AND gate 605 has a logic signal level of 0.
Therefore, the ROM5o1 and the decoder 607 are not pulled, and the μPC10
When the 0 μP C107 is updated to 3FFF, the AND gate 603 outputs the logic signal level '1'. At the same time, access to all RAM 6oa~613 and address 1
All four bits become valid, the loading of the program for initial program loading into the control storage device is completed, and the normal microprogram operation mode is entered.

〔Effect of the invention〕

According to the present invention, the following effects can be achieved.

Fixed memory for storing the program for loading the W-period program Q) The number of memory units used can be reduced, making implementation design easier.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of the system according to the present invention. Figure 2 is an operational flow diagram from power-on. Figure 3 is the microinstruction format. Figure 4 is the conventional microprogram loading method. FIG. 5 is an explanatory diagram of the microprogram loading method of the present invention with respect to FIG. 4, and FIG. 6 is an explanatory diagram of the operation of FIG. 102...External storage medium 107...Micro program counter 108...
Control storage device 601...Mode display flip-flop 602...
Microinstruction registers 603, 605, 606...AND gate 6
07...Decoder 621...Tri-state gate (,.

Claims (1)

[Claims] 1. The micro program storage section is configured with a variable memory and the initial program load program storage section is configured with a fixed memory. When the device is powered on, the initial program load program stored in the fixed memory is executed and the micro program is loaded. A microprogram control type information processing device into which a program is loaded is provided with a loading mechanism from a fixed memory to a variable memory, and an initial program load program is being loaded from the fixed memory to the variable memory, or An information processing device characterized in that the number of fixed memories to be used is not affected by the bit width of a microinstruction by having a mode display means for indicating whether a microprogram stored in a variable memory is being executed.