JPS62257544A - Display device for ram - Google Patents

Abstract

PURPOSE:To make it possible to refer to the content of an internal RAM while a microcomputer operates, by writing the data of the internal RAM in an external RAM and causing an address setting means and data displaying means to display the data. CONSTITUTION:A connecting means which can be connected with the terminal of an internal RAM mounted on a device to be tested using a microcomputer, external RAM 3 which stores the data written in the internal RAM 52, address setting means 4 for reading out data in the external RAM 3, and data displaying means 7 which displays data read out by the address setting means 4 are provided. An address iAD and data iDT from the internal RAM 52 obtained by means of a clip 53 are inputted to the external RAM 3 through a buffer 2. Therefore, the content of the internal RAM can be referred to under a condition where the microcomputer, RAM, etc., are mounted and while they are operated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a device for displaying the contents of a memory built into a microprocessor or the like.

[Prior Art 1] An in-circuit emulator as shown in FIG. 6 is known as this type of test device.

Reference numeral 61 denotes a control board serving as the device under test, which includes a microcomputer (hereinafter referred to as a microcomputer), a RAM (random access memory, hereinafter referred to as internal RAM), and the like. 62 is an IC socket having the same bin arrangement as the microphone installed in place of the removed microphone, and 63 is ■.

This is an IC plug inserted into the C socket 62.

64 is an interface port, and 65 is a test device.

With such a device, the test device 65 executes the program executed by the microcomputer, and at this time, the control board 6
By displaying the contents of the internal RAM on the test device 65 on the display section of the test device 65, tasks such as debugging programs on a control board that does not have an input/output device or an external storage device can be performed.

[Problem to be Solved by the Invention 1] However, in the case of the test device as described above, it is necessary to remove the microphone from the control board and provide a socket.

■Testing cannot be performed unless the operation of the device under test is stopped.

(2) The device under test 1 is small compared to the test device, making it difficult to write the wiring.

There were some drawbacks.

An object of the present invention is to provide a small and inexpensive display device that can refer to the contents of the RAM when the microcomputer, RAM, etc. are mounted on the device under test and while the microcomputer is operating.

[Means for Solving the Problems 1] The RAM display device of the present invention is an internal RAM display device installed in a device under test using a microcomputer.
connection means connectable to the terminal; and said internal RA
an external RAM that stores data written to M;
The device includes address setting means for reading out data in the external RAM, and data display means for displaying the data read out by the address setting stage.

1 Effect 1 According to the above configuration, the connecting means collects data from the terminal of the internal RAM mounted on the device under test, and the data is written to the external RAM. Then, when an address is set in the external RAM by the 7V address setting stage, data corresponding to the set address is retrieved, and this retrieved data is displayed on the data display means. ing.

[Embodiment 1] FIG. 5 shows the RAM display device and its usage method according to the present invention, and shows the inner Wb RA on the control board 51.
Various control signals are extracted from a clip 53 held between the M52 bins, and a data display 1a and an address setter 1b are provided on the display device.

FIG. 1 is a control block diagram showing one embodiment of the RAM display device 1. As shown in FIG.

After the address iAD and data iDT from the internal RAM 52 obtained by the clip 53 go through the buffer 72, they are input to the address bus EAD and the data bus EDT, respectively.
The data is input to AM 3 (herein referred to as external RAM). The address output by the address setter 4 for setting the address of the internal RAM 52 is inputted to the external RAM 3 via the address bus EAD after passing through the buffer 5, and
The data bus EDT is also input to a data display 7 via a register 6, and data corresponding to the address set by the address setter 4 is stored in the register 6 and displayed on the data display 7. It looks like this.

Also, the chip select signal C8 inputted at the same time is inputted to the register terminal of the register 6 and one input part of the OR date 8, and is also inputted to the date terminal G of the buffer 75 and the terminal OE of the external RAM 3 via the inverter 9. is input. The write signal WE is input to the other input part of the OR gate 8, and the write enable signal EWE from the OFF gate 8 is input to the write enable terminal W of the external gRAM3.
It is input to E. This off date 8 is provided to invalidate writing by the write signal WE when the chip select signal C8 is invalid. explain.

(1) When the internal fflsRAM is not accessed.

The timing at this time is shown in the time chart of FIG. In this case, the chip select signal C8 of the internal RAM 52
is at the "H" level, so the buffer 2 is in a disabled state and the buffer 75 is in an enabled state. As a result, the address set by the atlas setting device 4 is transferred to the external RAM via the buffer 5.
3, the data in the internal RAM 52 corresponding to the address is displayed on the data display 7 through the register 6.

As shown in the time chart, the address is Ah・RaB
, the display data will change from D^ to D accordingly.
Changes to B.

(n) When in write mode for internal RAM.

The timing at this time is shown in the time chart of figure tJJ3. At this time, the chip select signal C of the internal RAM 52
8 is at the "L" level, the buffer 75 is in a disabled state and the buffer 2 is in an enabled state. From this 1, external RAM M3 has internal RAM5.
The same address iAD and data iDT as in 2 are supplied. Furthermore, when the write signal WE goes to the L level, the write enable terminal WE of the external RAM 3 also goes to the L level, so at this time, the same data i as the internal RAM 52
DT is written to external RAM3. It should be noted that the contents of the renostar 6 retain the previous data while the chip select signal C37' is at the L level.

(■) When in read mode for iRAM.

The timing at this time is shown in the time chart of diagram Pt54. At this time, the write signal WE and the write enable signal EWE go to H level, and the mode is the same as the mode (II) above, except that the write signal is not written to the external RAλ·13.

As explained in the operating modes above, the internal RAM S
When writing to the device under test 51, the same data as the internal RAM 52 is written to the external RAM 31, and in other modes, data corresponding to the address set by the address setter 4 is displayed. The contents of the internal RAM 52 can always be referenced even when the internal RAM 52 is in operation.

Furthermore, if the above device is configured to consume low power, it can be operated using the power source of the device under test, and it can be made smaller by making the address setter 1 l a simple dip switch.

[Effect of the invention 1] According to the present invention, the data written in the internal RAM is written in the external RAM, and the written data is displayed by the address setting means and the data display means. It is possible to know the contents of the internal RAM during operation without removing the microcomputer from the board, and operations such as program debugging can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of one embodiment of the RAM display device of the present invention, FIGS. 2 to 4 are time charts showing the operation of the device in the tfS1 diagram, and FIG. 5 is the same as that shown in FIG. FIG. 6 is a diagram showing how to use the conventional device. 1... RAM display device, 1a... data display device,
1b... Address setter, 2, 5... Buffer, 3
...External RAM, 4...Address setter, 6...
・Renosta, 70.・Data display, death...off date, 9...inverter, 51...control board, 52...
- Internal RAM, 53...Clip. Patent applicant: Fujideniso Co., Ltd. agent Patent attorney: 2 people:

Claims (1)

[Claims] (1) A connection means that can be connected to an internal RAM terminal mounted on a device under test using a microcomputer, an external RAM that stores data written in the internal RAM, and an external RAM that stores data written in the internal RAM. 1. A RAM display device comprising: address setting means for reading out data; and data display means for displaying data read by said address setting means.