JPS6230112Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is directed to data recall (reading) necessary for checking the data contents stored in the storage means.
This invention relates to a small electronic calculator having a specific key for.

[Prior art and its problems] In recent years, small electronic calculators have been developed that have a programming function that allows operators to freely write program data (hereinafter referred to as programs) according to their own purposes, and are now widely used. ing. This type of computer is equipped with a specific key for checking the program, and each time this specific key is operated, a prewritten program is displayed one step at a time. Therefore, by operating this specific key, it is possible to check the program by checking whether there are any errors in the written program or by calling up a predetermined step of the program to correct or insert it.

However, in the above-mentioned conventional calculator, when the number of steps in the written program increases, the specific key must be repeatedly operated in order to call up the program of the desired step, and it takes a considerable amount of time to call up the desired program. There were drawbacks such as the need for time consuming and complicated key operations.

[Purpose of the invention] The present invention has been made in view of the above circumstances, and provides a small electronic calculator that can effectively perform data checking by changing the data recall state according to the pressing time of a specific key for data checking. The purpose is to provide

[Main points of the invention] The present invention provides a first method for continuously or intermittently displaying data recall based on the pressing time of a specific key prepared for displaying the recall of data stored in the storage means. As a set time for a second timer that measures a predetermined time to prevent key chattering by the timer and also measures the pressing time of the specific key, a first set time or a time shorter than the first set time is set. One of the second set times is selectively set according to the state of the flag. This flag is activated when the specific key is operated before the first timer finishes measuring a predetermined time to prevent chattering.
It also indicates whether or not this specific key has been pressed continuously for the time set for the second timer, and the time is set for the second timer according to the state of this flag. This enables continuous or intermittent data recall and display depending on the pressing time of a specific key while reliably preventing chattering.

[Embodiment of the invention] An embodiment of the invention will be specifically described below with reference to the drawings. In FIG. 1, reference numeral 10 is a key input section, which includes a numeric key 101 including a decimal point, a function key 102 for arithmetic operations, and a program used for calling a program and specifying a program number when writing. key 103, FST key 104 for sequentially displaying each step of the program when checking the program, BST key 105 for sequentially displaying each step of the program in the reverse direction, and program writing. , a mode switch for specifying each mode of execution, etc. are provided. The input information from the key input section 10 is sent to the arithmetic circuit 12 via the gate circuit 11.
is input. The arithmetic circuit 12 performs various arithmetic operations, as well as size comparisons, match comparisons, judgments on the presence or absence of data, etc., and the judgment results are provided to the ROM address section 13. The ROM address section 13 forms a microprogram control section together with a ROM (read only memory) 14, which will be described later, and when the ROM address section 13 specifies an address in the ROM 14, a predetermined microinstruction is output. That is, the ROM 14 supplies the next address designation signal NA that designates the next address to the ROM address part 13, and also supplies the row address designation signal U and the column address designation part 16 to the RAM (random access memory) 15. A column address designation signal L is applied through the RAM 15 to designate a register. The above row address designation signal U
specifies a register constituting the RAM 15, and the column address designation signal L usually specifies a predetermined digit of the register. Therefore, when specifying multiple register digits, supply the column address of the lower digit of the digit to be specified to the column address specifying section 16, and match this address with the column address of the upper digit of the digit to be specified. This is done by sequentially stepping up to Further, the ROM 14 is configured to provide a code signal CO to the arithmetic circuit 12 via a gate circuit 17. Above RAM1
As shown in FIG. 2, numeral 5 is composed of an X register, an A register, a C register, an arithmetic register (not shown), a register having a key sampling count digit, and the like. Display data is stored in the X register, and program data, which will be described later, is stored in digits 1 and 2 of the A register. In addition, time count data is stored in the first digit of the C register in order to prevent so-called chattering, which occurs when various keys of the key input section 10 are pressed, even though the key is pressed once. ~3rd digit
Count data for detecting whether the FST key 104 is pressed intermittently or continuously is stored, and a flag is written in the F digit when the FST key 104 is pressed continuously. Therefore, the above
The arithmetic numbers and operands stored in the arithmetic registers of the RAM 15 are supplied to the arithmetic circuit 12 via gate circuits 18 and 19, respectively, where arithmetic operations are performed, and the results of the arithmetic operations are written into the arithmetic registers again. In addition, the program data in the 1st and 2nd digits of the A register is used for program storage via the gate circuit 20.
The display data written in the RAM 21 and stored in the X register is sent to the display unit 23 via the gate circuit 22 and displayed. Furthermore, during key sampling to detect whether or not a key operation has been performed on the key input section 10, the count data of the key sampling count digit is supplied to the decoder 25 via the gate circuit 24 and decoded. The signal is applied to the rear key input section 10.

On the other hand, the program storage RAM 21 stores a program created by the operator as shown in FIG.
1 program data is passed through the gate circuit 26.
After being temporarily stored in the first and second digits of the A register of the RAM 15, the program is executed in the arithmetic circuit 12, although it will not be described in detail. In this example, the above program data is converted to 2 according to the conversion table shown in Figure 4.
It is expressed using digit (row, column) codes. For example, for program data “P1” (1,
1), "X" is represented by the code (4, 3). Furthermore, when checking the program written in the program storage RAM 21, the program data written in the first and second digits of the A register is supplied to the display code storage ROM 27 via the gate circuit 28 and converted into a display code. The data is converted and written to the display X register of the RAM 15 via the gate circuit 28 again. The display code storage ROM 27 converts the program data stored in the program storage RAM 21 into a display code for displaying in a predetermined format, as shown in the conversion table of FIG. For example, program data ``Min1'' is converted into a display code corresponding to ``1-1'' display, and program data ``X'' is converted into a display code corresponding to ``F1-3'' display.

In addition, the operation signal is output from ROM14.
OP is given to the instruction decoder 29, which causes the instruction decoder 29 to output the gate circuits 11, 17 to 20, 2.
Gate control signals A to J that control opening and closing of each gate circuit 2, 24, 26, 28, and 31 and arithmetic circuit 1
2, a subtraction instruction Sub is outputted to the program counter (PC) 30, and a control signal K is given to the program counter (PC) 30 to control the increment or decrement of the count contents. From the program counter 30, the gate circuit 31
A program address designation signal is output to the program storage RAM 21 via the program storage RAM 21, and the address of the program storage RAM is designated.

Next, the detailed operation of the program check according to the present invention constructed as described above will be explained with reference to FIGS. 5 to 7. First, a case will be described in which a program check is performed while intermittently operating the FST key 104 as shown in FIG. 6a.
First, in step _S1 , a code signal "10" is written in the first digit of the C register for time counting to prevent chattering. That is, the first digit of the C register is designated by the row address designation signal U and column address designation signal L from the ROM 14. and above
The code signal "10" output from the ROM 14 is written to the first digit of the C register via the gate circuit 17 and the arithmetic circuit 12, and the process advances to the next step _S2 .
Processing S ₂ performs key sampling, and is the same as above.
Key operations are performed by supplying count data of the key sampling count digits of the RAM 15 to the key input section 10 via the decoder 25, and determining whether or not there is output data from the key input section 10 at that time. It is to judge whether or not it was successful. When no key operation is performed, the count data of the key sampling count digit is set to "+1".
Then, proceed to step _S3 . step
At _S3 , the contents of the first digit of the C register are supplied to the arithmetic circuit 12, where it is determined whether the contents are "0" or not. Now, since the first digit of the C register above is "10", it is determined that it is not "0".
This determination result is applied to the ROM address section 13 together with the next address signal NA output from the ROM 14, address modification is performed, and the next step _S4 is addressed. In step _S4 , the content of the first digit of the C register is set to "-1". That is, the arithmetic circuit 12 is supplied with the contents of the first digit of the C register and the code signal "1" output from the ROM 14, and in accordance with the subtraction instruction Sub output from the instruction decoder 29, "C ₁ -
1'' is subtracted. Therefore, the content "10" in the first digit of the C register is subtracted by "-1" to become "9" and the process returns to step _S2 . In process _S2 , the key sampling process is performed in the same manner as described above using the updated count data of the key sampling count digits. Processing S ₂ , step S ₃ , and step S ₄ are similarly executed sequentially, and when the content of the first digit of the C register becomes "0" in step S ₄ , processing S ₂ and step S ₃ are executed alternately. will be done. In other words, the process S ₂ , step S ₃ or step S 2 continues until a key operation is performed.
_S4 is executed sequentially. Therefore, the first digit of the above C register becomes "0", and processing 2, step
When the FST key 104 is operated as shown in FIG. 6a while steps _S3 are being executed in sequence, the key is present in _{step S2} and the process proceeds to step _S5 . In step _S5 , similarly to step _S3 , it is determined whether the first digit of the C register is "0". At this time,
Since the first digit of the C register is "0", the process advances to step _S6 , where a key determination process is performed to determine what key is operated on the key input section 10. in this case,
Since the FST key 104 has been operated as described above, the process advances to step _S7 . In addition,
If a key such as a numeric key or a function key is operated, the process advances to step _S8 , where numeric or arithmetic processing is performed, and when that process is completed, the process advances to step _S1 and process _S2 , where key sampling is performed in the same manner as above. will be held. Therefore, in step _S7 , it is determined whether a flag indicating that the FST key 104 has been pressed continuously is written in the F digit of the C register.
In other words, the F of the C register specified by the ROM14
The contents of the digit and the code signal output from the ROM 14 are supplied to the arithmetic circuit 12, and it is determined whether or not the result of subtracting the two is "0". Since the flag has not yet been written in the F digit of the C register, the process advances to step _S9 . In step S ₉ ,
"0" is written in the 2nd to 3rd digits of the C register for detecting whether the FST key 104 is pressed intermittently or continuously. Then, in the next step _S10 , the count value of the program counter 30 is incremented according to the control signal K from the instruction decoder 29. So, now if the above count value is "0", it will increment by "1" and become "1".
Then, proceed to the next step _S11 . In step _S11 , the count value of the program counter 30 is transferred to the program storage RAM 2 via the gate circuit 31.
1 is applied to designate an address and read out the program contents at that address.
Therefore, since the count value of the program counter 30 is "1", the program storage RAM 21
address "1" is specified, and as shown in FIG. Written in the eyes. Furthermore, in the next step _S12 , the contents of the first and second digits of the A register written in the above step _S11 are stored as a display code via the gate circuit 28.
Supplied to ROM27 and converted to display code
Written to the X register of RAM15. At step _S13 , the display data of the X register is supplied to the display section 23 via the gate circuit 22, and the program step 1 is displayed as shown in FIG. Next, the process proceeds to step _S14 , where "0" is written in the F digit of the C register, and the process proceeds to step _S1 again. Processing S ₂ , step S ₃ or step S ₄ is then executed in sequence until the next key operation is performed.

Furthermore, when the FST key 104 is operated as shown in FIG. 6a, each step is executed in the same manner as described above, and in step _S10 , the count value of the program counter 30 is incremented to "2", and the program memory is stored as shown in FIG. Program contents of address 2 stored in RAM 21 "Min1"
(Step 2) is called and the step 2 of the program is displayed as shown in FIG. Similarly, the contents of each step of the program written as shown in FIG. 3 are sequentially displayed as shown in FIG. 7 each time the FST key 104 is operated.

Next, the case where the FST key 104 is continuously pressed as shown in FIG. 6b will be explained. It is assumed that the count value of the program counter 30 is "0" at this point. When the FST key 104 is initially pressed, steps _S5 to _S7 and step _S9 are performed, as in the case of intermittent operation of the FST key 104 described above.
is executed, and in step _S10 , the count value of the program counter 30 is incremented to "1". And step S ₁₁ to step
_S14 is executed and the display of step 1 is performed.
When the process of step _S14 is completed, the process proceeds to step _S1 , where a code signal "10" is written in the first digit of the C register, and the process proceeds to the next process _S2 . At this point FST
Since the key 104 is pressed continuously, the process
S ₂ key sampling shows a key and steps
Proceed to _S5 . At step _S5 , since the content of the first digit of the C register is "10", it is determined that "C ₁ ≠0", and the process proceeds to step _S15 . In step _S15 , it is determined whether or not the pressed key is the FST key 104 based on the key output data output from the key input unit 10 corresponding to the pressed key and the count data of the key sampling count digit in the RAM 15 at that time. be judged. Here, since the FST key 104 is continuously pressed, the process advances to the next step _S16 . Note that if the key other than the FST key 104 is a key other than the FST key 104 in the state of "C ₁ ≠ 0", the process advances to step S ₁ and chattering prevention is performed. Step _S16 is C register 2-3
The content of the digit is incremented by "+1", and it is detected whether the FST key 104 has been pressed continuously based on whether or not a carry occurs as a result. That is, the contents of the second to third digits of the C register addressed by the ROM 14 and the code signal "1" are supplied to the arithmetic circuit 12, and the two are added. If the contents of the second and third digits of the C register are "0", then "+
1” and becomes “1”. Since no carry occurs here, the process proceeds to step _S1 above. Similarly, step S ₁ , processing S ₂ , step S ₅ , step S ₁₅ ,
Each step of step _S16 is executed in a circular manner, and the contents of the second and third digits of the C register are sequentially counted up. And this C register 2
When the content of the third digit is counted up to "99" and further incremented by "+1", a carry occurs and the process proceeds to the next step _S17 . In other words, if the FST key 104 is not pressed for longer than the time required for the second and third digits of the C register to be counted up from "0" to "100" in step _S16 , the key will not be pressed continuously. become. In the next step _S17 , the FST key 104 is pressed continuously, so that a flag is written in the F digit of the C register, and the process advances to step _S7 . At step _S7 , since the flag has been written in the F digit of the C register, the process advances to the next step _S18 . C at step S ₁₈
“0” is written to the second digit of the register, and in the next step _S19 , “9” is written to the third digit of the C register.
is written. Therefore, in steps _S18 and _S19 , "90" is preset in the second and third digits of the C register. Then, steps _S10 to _S14 are executed as described above, and step 2 of the program is displayed. Since the FST key 104 remains pressed as shown in FIG. 6b, step S ₁ , process S ₂ ,
Step S ₅ , step S ₁₅ , and step ₁₆ are executed in a cycle. At step _S16 , the 2nd and 3rd digits of the C register are filled with the above steps.
Since "90" is preset in steps S ₁₈ and S ₁₉ , a carry occurs from the second to third digits of this C register in one-tenth of the previous time. and step S ₁₇ , step S ₇ , step ₁₈ , step S ₁₉ , step S ₁₀ to step S ₁₄
is executed as above, and step 3 of the program
is displayed. Similarly, FST key 104
While the button is continuously pressed, the contents of the program are displayed one step at a time as shown in FIG. 6b.

In this embodiment, the FST key 104 is operated to advance and check the program in the forward direction. For example, if you want to advance in the opposite direction during the progression, press the BST key 105. Of course, the program counter 30 may be operated to decrement the count value of the program counter 30 and perform backward stepping. In short, the present invention may be modified in various ways as long as it does not depart from the gist of the invention.

[Effects of the invention] As explained in detail above, according to the present invention, when checking data, data call display can be performed continuously or intermittently depending on the pressing time of a specific key for data call display. When calling the desired data, at first, the data is called continuously by holding down the specific key mentioned above, and when the desired data is reached, the specific key is operated intermittently to ensure a reliable and quick process. The desired data can then be called up. In particular, the first clocking means (C register C ₁ ) clocks a predetermined time to prevent key chattering, and the state of the flag (C register F)
Since the setting time of the second clock means (C registers C ₂ and C ₃ ) is selected and set accordingly, chattering can be reliably prevented and data can be called continuously or intermittently using a specific key. will be accomplished. In this way, desired data can be called up quickly and reliably by simple key operations, which is very effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.
Figure 2 is a register configuration diagram in the RAM shown in Figure 1.
1 is a program storage state diagram of the program storage RAM, FIG. 4 is a conversion table showing the relationship between each command of the program and the display format, and FIG. 5 is a flowchart for explaining the operation of the same example.
6a and 6b are state diagrams showing the relationship between FST key operations and display of program contents, and FIG. 7 is a diagram showing the display state of program contents on the display section of FIG. 1. 10...Input section, 104...FST key, 10
5...BST key, 12... Arithmetic circuit, 13...
ROM address section, 14...ROM, 15...
RAM, 21...RAM for program storage, 23...
...Display unit, 25...Decoder, 27...Display code storage ROM, 29...Instruction decoder, 30...Program counter.

Claims (1)

[Scope of utility model registration request] A key input means having a specific key and at least a plurality of keys for inputting data, a storage means for storing a plurality of data input from the key input means, and a method for specifying an address of the storage means. address specifying means, address updating means for updating the address of the address specifying means, and data for reading out data stored in the storage means based on the address specification of the address specifying means in response to instructions from the specific key. a reading means, a display means for displaying the data read out from the storage means by the data reading means, a first timer for measuring a predetermined time to prevent key chattering, and a first timer for measuring a predetermined time for preventing key chattering; Second timer
When the specific key is operated before the clocking means and the first clocking means finish clocking a predetermined time to prevent chattering, and the second clocking means is interrupted for a preset time. a detection means for detecting that the button has been pressed; a flag storage means for storing a flag based on the detection signal of the detection means; a time setting means for setting a first set time or a second set time shorter than the first set time; and a time setting means for setting the first set time or a second set time shorter than the first set time; The device is characterized by comprising means for causing the address updating means to update the address every time the set time of item 2 is counted, and controlling the data reading means to continuously read data from the storage means. A small electronic calculator.