JPS6232646A - Manufacture of gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To simplify manufacturing processes, by simultaneously diffusing and forming a p-type layer and a p-type emitter layer, which have high impurity concentration, on a p-type base layer. CONSTITUTION:Oxide films 16 are formed on both main surfaces by a thermal oxidation method. Gallium is diffused in both main surfaces, and a p-type base (pB) layer 12 is formed. The gallium diffused layer on the opposite surface with respect to the pB layer 12 is polished and removed. Then the oxide film 16 is formed again on the removed part. A part of the film 16 is selectively removed. Phosphorus is selectively diffused in both entire main surfaces or the removed part, and an n-type emitter (nE) layer 15 and n<+> layers 13, which are arranged in parallel in an island shape, are formed. Then the oxide film 16 is formed again, and a part of it is selectively removed. With the remaining oxide film 16 as a mask, the pB layer 12 is selectively etched away, and a specified step structure is provided between the layer 12 and the nE layer 15. The oxide film 15 is formed so as to serve the role of the driving diffusion of the nE layer 15. Then gallium is diffused and a p-type emitter (pE) layer 14 is formed on one side. A p-type high-impurity concentration layer 20 is simultaneously formed on the pB layer 12. A part of the oxide film 16 at the junction part between the nE layer 15 and the pB layer 12 is selectively removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a gate turn-off thyristor (hereinafter referred to as GTD).

[Conventional technology]

FIG. 1 shows a cross section of a GTO shown in Japanese Patent Application Laid-Open No. 59-9988 as a conventional example, in which one RL emitter layer corresponds to one RL emitter layer among a number of GTOs arranged in parallel in an island shape on a semiconductor substrate. FIG. 3 is a partial perspective view of a segment.

That is, in the conventional example shown in FIG.
B is an n+ type formation diffusion layer 4 selectively formed on the main surface of the 18 layer 1 opposite to P-2, and a p type emitter (p) layer formed in line with this n+ type diffusion layer side. , 5 are n-type emitter (n 2 ) layers selectively formed on the main surface of the two layers 2 and arranged in parallel in a large number in the form of islands, 6
is an oxide film that electrically protects the junction E EE between the first layer 5 and the second layer 2, and 7, 8, and 9
are the above “E H5+ P s layer 2 and I
'E R' is a cathode electrode, a gate electrode and an anode electrode formed by ohmic contact.

The conventional GTO is configured as described above and operates as follows. Namely.

First, in order to turn the OFF state into the ON state, the pn junction between the 18th layer 5 and the 2nd layer 2 is sequentially/circularly connected.
Holes are injected from p-2 to 18 layer 5, and electrons are injected from layer 5, and by this transistor action, they are supplied from n-5 to layer 1 through Ps layer 2. In order to generate excess electrons and neutralize them, the same amount of holes are injected from p-4, and the excess holes are supplied to the two layers 2, which supply current to each other's base layers. , 28
Even if the gate circuit to layer 2 is opened, the on state will continue to be maintained.

In addition, in order to change from the on state to the off state, a negative voltage is applied to the gate polarization 8, and the voltage from n-1 to l"E'!i':
5' The flowing holes are transferred to the gate electrode 8 when passing through p-2.
One by one, one bow is drawn out, starting with the one that passes the closest part, and
By concentrating the electrons on the center of the 5th layer 5, injection of electrons from the n-5 electrons into the 2nd layer 2 is prevented and the electrons are turned off.

[Problem that the invention seeks to solve]

In the case of the GTO with the conventional configuration, the turn-off characteristics are determined by how efficiently the holes in the second layer 2 are removed by the G71 current, and are particularly strong against the lateral resistance of the second layer 2. This lateral force resistance depends on the distance of the current path in the bilayer 2 and the p-2 impurity concentration.

On the one hand, it is important to diffuse the second layer 2 with a predetermined impurity concentration in the manufacturing of this type of GTO, and on the other hand, as the current capacity of GTO increases, the semiconductor substrate also becomes more important. There is a tendency for the diameter to become larger and larger, and in this case, the gate signal is supplied from the gate lead wire that is in contact with the gate electrode 8. It is estimated that the first layer 5 near the contact part of the gate lead wire will be turned off because the distance between them will become larger and the potential difference will become larger.
Since the anode current is concentrated in n-5, which does not reach the off state, there is a risk that this current concentration may cause damage to the nearby area. Consideration has been given to forming a ρ-shaped layer.

In view of the above-mentioned conventional circumstances, it is an object of the present invention to provide a simplified method for manufacturing a GTO for forming a p-type high impurity concentration layer in a p-layer.

[Means for solving problems]

The GTO manufacturing method according to the present invention is such that a p-type layer with a high impurity concentration and a p- layer on two layers are simultaneously formed by diffusion.

[For production]

Therefore, in the method of the present invention, the manufacturing process can be simplified by simultaneously forming the p-type layer with a high impurity concentration on the Ps layer and the 9th layer by diffusion.

〔Example〕

An embodiment of the GTO manufacturing method according to the present invention will be described in detail below with reference to FIGS. 1(a) to 1(e).

FIG. 1 is a cross-sectional view showing a method for manufacturing a GTO to which this embodiment is applied in order of steps.

In this embodiment method, first, as shown in FIG. 1(a), an n-type silicon semiconductor substrate 11 having a specific resistance of about 120 Ω-cm is used, and an oxide film is formed on both main surfaces of the semiconductor substrate 11 by thermal oxidation. After forming 16, on both main surfaces,
Gallium is diffused to form a 28 layer 12 so that the surface concentration is approximately 1 to 2 Xl018/crn', and as shown in FIG. After removing it, oxidize 1111B again on the same area.
After forming and selectively removing a part of it by photolithography, phosphorus is selectively diffused into the entire amphiphilic surface or the removed part so that the surface concentration is about 2 to 5 XIO20/cm''. One layer 15 arranged side by side in a large number in the form of an island.
．． and form the n1 layer 13.

Next, as shown in the same figure (C), the oxide film is formed again! 6
After forming and selectively removing a part of it by photolithography, using the remaining oxide film 16 as a mask, the second layer 12 is selectively etched away by about 30 mm.
After providing a predetermined step structure with the EJi 15 and forming an oxide film 16 which also serves as a drive diffusion for the N5 layer 15, as shown in FIG.
18/am', gallium is diffused to form two layers 14 on one side and two layers 12 on the other side.
Seven p-type high impurity concentration layers 20 are simultaneously formed on top of each other, and as shown in FIG. Finally, a cathode electrode 17 is formed on the n-layer 15, and a high impurity concentration layer (n-type layer) is formed on the second layer 12.
20 on the gate electrode 18. and an anode electrode 19 is selectively deposited with aluminum on the two layers 14,
It is completed by making ohmic contact.

In this manufacturing process, the surface concentration of the two silicon-etched layers 12 has been reduced to about 5X 1017/am'', so the effect of diffusing the p-type impurity to increase the surface concentration is large; -, gallium is diffused using the high concentration diffusion layers of the 1st layer 15 and the n+ layer 13 as a mask, but after selectively removing a part of the oxide film 18 by photolithography, the high concentration p-type It is also possible to diffuse impurities, and furthermore, after driving diffusion of one layer 15,
When evaluating the lateral resistance E B of the second layer 12 and forming the p-type high impurity concentration layer 20 on the second layer 12, it is also possible to carry out forced diffusion of nEFls.

In the above embodiment, a GTO in which the anode is short-circuited has been described, but it goes without saying that the present invention can also be applied to a GTO having an anode-short-circuited structure in which the two layers 14 are diffused over the entire surface.

〔Effect of the invention〕

As described in detail above, according to the method of the present invention, p-type impurities are selectively diffused from the bidirectional side of the semiconductor substrate, and the p-type layer with high impurity concentration on the p-layer and the p-layer B
Since the GTO and E are formed at the same time, the turn-off characteristics of this type of GTO can be improved and the manufacturing process can be simplified.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are sectional views showing an embodiment of the GTO manufacturing method according to the present invention in the order of steps, and FIG. 2 is a partially sectional perspective view of a conventional GTO. 11...n-type base layer (1 layer), 12...p-type base M (p layer), 13...n+ calendar, 14...
P-type emitter layer (pF!F), 15...” N-type emitter layer (1 layer), 16E
E... Oxide film, 17... Cathode electrode, 18...
...Gate electrode, 19...Anode electrode, 20...
...P-type high impurity concentration layer. Agent: Masuo Oiwa Figure 1, Figure 1, Figure 2, Procedure amendment (voluntary) Date of 1939, Chief of the Office of the Governor's Palace 1, Indication of the case Patent application No. 172622, 1939
, Name of the invention Method for manufacturing gate turn-off thyristors 3, Relationship with the amended case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, agent address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, correct the correction target. that's all

Claims (1)

[Claims] a p-type emitter layer, an n-type base layer, a p-type base layer,
It has a four-layer structure in which a large number of n-type emitter layers are arranged in parallel in the form of islands and are formed adjacent to each other in sequence, with an anode electrode on the p-type emitter layer and a gate electrode on the p-type base layer. In a gate turn-off thyristor in which a cathode electrode is formed on each n-type emitter layer, the surface of the p-type base layer, which is one main surface, is dug down to form a stepped structure between the gate electrode and the cathode electrode, and this A method for manufacturing a gate turn-off thyristor, characterized in that a p-type layer with a high impurity concentration on a dug-out p-type base layer and a p-type emitter layer on the other main surface are simultaneously formed by diffusion.