JPS6232736A - Error protecting circuit - Google Patents

Abstract

PURPOSE:To speed up an output response when an error ratio in a transmission line is small by selecting input data to an error protecting means or an output from the error protecting means in accordance with the error ratio in the transmission line. CONSTITUTION:Data read out from a digital pulse string received on a signal line 101 are inputted to the error protecting means 13 for preventing output information from the generation of an error due to the error of the transmission line. The output signal on a signal line 102 and the input signal on the signal line 101 are inputted to a selecting means 12 and any one of said signals is selected by the selecting means 12 in accordance with the output state of an error counting means 11. When the error ratio on the transmission line is large, signal on the transmission lien 102 is selected, and in case of a small error ratio, the signal on the signal line 101 is selected. Consequently, an output response can follow up the change of the transmitted signal without dealy when the error ratio on the transmission line is small, so that the output response can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an error protection circuit used in a digital transmission device, and more particularly to error protection in a transmission path of a DC level signal that does not change in a short time.

(Prior Art) Conventionally, a shift register has been used as a protection circuit to protect against errors in the transmission path, and the output state is changed only when the data information changes continuously for a preset number of times. Error protection circuits configured to vary are known. FIG. 3 is a block diagram illustrating an example of an error protection circuit according to the prior art. In FIG. 3, 31 is a shift register, 32 to 35 are D-type flip-flops, and 36 is a shift register.
39 are NAND gates, and 40 is an R8 type flip-flop.

In FIG. 3, data is input onto a signal line 301, and a clock synchronized with the data is input onto a signal line 302. For example, it is assumed that the digital signal transmitted to the receiving section constitutes a frame, and an information signal is inserted into the frame to establish synchronization. In this case, the data on signal line 301 is in a synchronous state, and signal #
This corresponds to the data read out from the digital signal pulse train by the clock on 302. The shift register 31 is 4
NAND gates 36 and 3
I am looking for it by 7. The output of NAND game 1-36, 37 is R configured by NAND game) 38.39
It is input to the type 8 flikpflokpu 40, and the signal lN303
Sends an output signal to the top.

The shift register 31 has four D-type flip-flops 32.
.about.35, the output state of the R8 type flip 70 tube 40 changes if the state in which the signal read from the digital signal pulse train changes four times in a row.

(Problems to be Solved by the Invention) The above-mentioned conventional error protection circuit for a transmission line outputs information by reading the error information when the error rate of DC changes in the transmission line is large during digital signal transmission. It has the advantage of being able to prevent errors in the transmission, but it has the disadvantage that when the transmitted signal changes, there is a delay equal to the number of stages in the shift register circuit before the changed information is output as an output signal. there were.

An object of the present invention is to add error counting means and selection means to the error protection means, and select input data to the error protection means or output from the error protection means according to the error rate of the transmission path. By eliminating the above drawbacks, when the error rate of the transmission path is small, it is possible to follow changes in the transmitted signal without including delay, while when the error rate is large, errors in the output information due to erroneous information can be corrected. An object of the present invention is to provide an error protection circuit configured to prevent errors using protection means.

(Means for Solving the Problems) The error protection circuit according to the present invention is configured to include error counting means, error protection means, and selection means.

The error counting means is for monitoring errors in the transmission path.

The error protection means is intended to prevent errors in output information caused by reading of erroneous information due to errors in the transmission path.

The selection means receives the output information of the error protection circuit and the input information of the error protection means, and selects either the input information or the output information according to the output information of the error counting means.

(Embodiment) Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an error protection circuit according to the present invention. In FIG. 1, the error protection circuit is composed of error counting means 11, selection means 12, and error protection means 13 having the same configuration as a conventional error protection circuit.

In FIG. 1, data read from a digital pulse train received on signal 1s101 is input to error protection means 13 for preventing errors in output information due to errors in the transmission path. The output signal on the signal a102 and the input signal on the signal line 101 are input to the selection means 12, and the error counting means 1
Depending on the output state of 1, the selection means 12 selects one of the above. When the error in the transmission path is large, the signal on the signal line 102 is selected, and when the error is small, the signal on the signal line 101 is selected.
The upper signal is selected.

FIG. 2 is a block diagram showing a detailed example of the error protection circuit shown in FIG. 1. In FIG. 2, 21 is an error counting means, 22 is an SR type rough flip-flop, 23 is a NAND gate, 24 is a NAND gate, and 25 is an R8 type rip-flop.
26 is a selection means, and 27 to 30 are D-type flips 7.
0 and 41.42 are NAND gates.

In FIG. 2, the error protection circuit includes error counting means 21;
Shift register 22, NAND gates 23 and 24,
It is composed of an R.8 type flip-flop 25 and selection means 26. The error counting means 21 monitors the error rate of the transmission path, and when the error rate exceeds a set value, the output state changes.

The shift register 22 has four D-type flip-flops 27.
It consists of ~30. The data on signal line 201 and the clock on signal line 202 are equivalent to the data and clock in FIG.

The data on the signal line 201 is read into the shift register 22 by a clock synchronized with the data.

The outputs Q and Q of the flip-flops 27 to 30 constituting the shift register 22 are respectively connected to NAND gates)2.
In addition to 3.24, the inverse of the logical product is obtained, and the output thereof is input to the R8 type flip-flop 25 constituted by two NAND gates 41 and 42. When the state of the data on the signal line 201 changes four times in succession, the output of the R8 type flip-flop 25 changes, and the state of the signal on the signal line 203 changes. When the error rate of the transmission path is small (in this case, the signal outputted from the error counting means onto the signal line 203 is at 1H" (high) level, and at this time the signal outputted from the selection means 26 onto the signal line 206 , the signal on the signal line 204 is directly output. When the error rate increases and exceeds the set value, the signal output from the error counting means 21 to the signal line 203 changes to "L" (low) level. , the signal outputted from the selection means 26 to the signal line 206 is the output of the R8 type flip-flop 25.0 (Effects of the Invention) As explained above, the present invention provides an error protection means with a selection means on the counting means. By adding this and selecting input data to the error protection means or output from the error protection means according to the error rate of the transmission path, when the error rate of the transmission path is small, changes in the transmitted data can be ignored. On the other hand, there is no delay, the output is like a response, and when the error rate is large, the output of error information due to errors in the transmission path can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of an error protection circuit according to the present invention. FIG. 2 is a block diagram showing a detailed example of the error protection circuit shown in FIG. 1. FIG. 3 is a block diagram showing an example of an error protection circuit according to the prior art. 11.21...Error counting means 12.26...Selection means 13...Error protection means 22.31...Shift register 23.24.37-39,41,42...NAND gate

Claims (1)

[Claims] error counting means for monitoring errors in the transmission path; error protection means for preventing errors in output information resulting from reading of error information due to errors in the transmission path; Input information of the error protection means is input, and selection means is provided for selecting either the input information or the output information according to the output state of the error counting means. Error protection circuit.