JPS6233096U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit for driving a display device using P display devices arranged in m rows and n columns according to an embodiment of this invention, and FIG.
A block diagram showing a circuit for driving five groups of EDs, and FIGS. 3 and 4 are timing charts showing the timing of predetermined portions in FIG. 2. FIG. 5 is a block diagram showing a circuit for driving a display device according to a conventional example of this invention. In the figure, 1 is the central processing unit (CPU),
4 is a read-only memory (ROM), 5 is a timing generation circuit, 6 is a device driver, 7
is the display device, 9 is the device driver, 1
0 is a time division bus holding circuit, 11 is an output side latch circuit, and 12 is a time division timing generation circuit. The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] P time-division bus holding circuits that receive and hold data from the central processing unit; a timing generation circuit that provides timing for outputting a signal to one of the P time-division bus holding circuits; One read-only memory that receives a signal from one time-division bus holding circuit instructed by the circuit in accordance with the timing of the timing generation circuit and converts the data, and P output sides that receive output signals of this read-only memory. a latch circuit, and a time division timing generation circuit that specifies the timing for sending the output signal of the read-only memory to one of the P output latch circuits;
A drive consisting of P device drivers that receive signals from this one designated output side latch circuit, and a display device that receives and displays signals from the device drivers in accordance with the timing of the timing generation circuit. A display device characterized by being equipped with a circuit.