JPS623481A - Memory control device - Google Patents

Abstract

PURPOSE:To access to plural memories for one access request by receiving an address signal to specify a memory cell and writing an input data even to other memory cell stipulated beforehand besides a memory cell. CONSTITUTION:A memory matrix 1 is composed of the memory cell of 5X5=25 bits. Input data a0-aS are selectively connected to nine pieces of data input of respective cells of the matrix 1 by an address decoder 3b, and the selecting action is executed by the output of address buffers 2a and 2b. The output of buffers 2a and 2b is supplied to an address decoder 3a, and respective pairs of the prescribed bit output selecting lines out of an output selecting line 5 are activated. Simultaneously, a writing clock from a decoder 3a is supplied to the selected memory cell. Thus, only by the access of one special memory cell, other memory cell stipulated beforehand related to this can be simultaneously accessed.

Description

TECHNICAL FIELD The present invention relates to a memory control device, and more particularly to a memory control device suitable for use in pattern processing circuits, image processing circuits, and the like.

In conventional memory control systems, data is written to and read from one specific memory cell in one memory access. Here, in fields such as pattern processing and image processing, it is often very convenient to process and handle the memory contents of a group of memory cells related to beans at once. When accessing the contents of each memory in the memory cell group, it is necessary to sequentially perform serial access. Therefore, there is a drawback that access processing time increases.

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a memory v control device that allows access to a plurality of predetermined memory cells in response to one access request.

and rg3oυ1 claw The memory 111 control device according to the present invention receives an address signal for specifying one memory cell in a memory matrix and inputs input data to other predetermined memory cells in addition to this one memory cell. The memory cell is characterized in that it includes a write address decoder means for setting the memory cell in a writable state, and an input data supply means for supplying corresponding input data to each memory cell set in a writable state.

In addition to the above configuration, another memory control device of the present invention further includes:
It is characterized in that it includes read address decoder means for receiving the address signal and placing the one memory cell and the predetermined other memory cell in a state in which stored data can be read.

1 blind 1 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, where the memory matrix 1 consists of a group of 5×5=25 bits of memory cells, and data reading and writing can be performed from aO to A0 through one access, as shown in FIG. It is assumed that this is performed using 9 bits of a8. As an example of how data is read and written in one access, as shown in FIG. 4, in addition to memory cells (Xi, Yl), (X2.Yl), (X2. YO),
(Xl,,YO).

(XO, YO), (XO, Yl), (X
O,Y2).

The memory cells (Xl, Y2'') and (X2.Y2) can also be accessed.Also, as shown in FIG.
Memory cell (×2°Yl) for one address signal
Besides (X3.Yl), (X3.YO).

, (X2.YO), (Xi,YO), (
XI, Yl').

(Xl, Y2), (X2.Y2) and (X3
．． Each memory cell of Y2) can also be accessed.

That is, this is an example in which one memory cell can be accessed simultaneously by each of the surrounding cells.

It is assumed that each memory cell of the memory matrix 1 has a D-type flip 70 tube configuration, as shown in FIG. The 9-bit parallel input data lines aO to a8 are selectively electrically connected to 9 lines (9 bits) of the data output (D input in FIG. 2) of each cell of the memory matrix 1 by the address decoder 3b. It is designed to be connected to

This selection operation of the address decoder 3b is performed by the outputs of the address buffers 2a and 2b.
A 3-bit Y address and a 3-bit address are supplied to each address buffer 2a and 2b, respectively, and the center memory cell (aO ) is now specified.

The outputs of the address buffers 2a and 2b are also supplied to an address decoder group 3a, which receives the outputs of both address buffers and selects nine sets of bit output selection lines 5, each set of 25 bits. Among them, a predetermined bit output selection line of each set is activated. For example, bit output selection J! (In the bottom set of 1!!5, the line corresponding to the aO bit is activated, in the set above it, the line corresponding to the a1 bit is activated, and in the top set, the line corresponding to the a8 bit is activated. It has become so.

Further, a write clock is supplied to this address decoder 3a, and the current X of the 25-bit memory cells is
This write clock is selectively supplied to 9-bit memory cells corresponding to 8 bits aO to a determined by the , Y address.

The 25-bit output line 6 of each memory cell of the memory matrix 1 is input to a multiplexer circuit 4 consisting of a group of nine 1/25 multiplexers.
This is for selecting a specific one of the bits and making it the memory output aO to a8. In this case, each set of bit output lines 5 of the address decoder 3a corresponds to one
The memory cell output corresponding to the activated bit line of bit output line 5 in each set is selected and output.

In this configuration, writing of input data will be explained. The X and Y address signals specifying the back center cell (aO) of the write memory cell are sent to the address buffers 2b and 2.
input to a. At this time, the R/W signal enables the address decoder 3b, and the address decoder 3bT- selectively distributes the 9-bit input data aO to a8 to 9 of the 25-bit memory cells of the memory matrix 1. This distribution is made into a center cell (aO) specified by the X and Y address signals and eight cells (a1 to a8) surrounding it. At the same time, the write clock is output from the address decoder 3a to the selected 9
The 9-bit input data is simultaneously written into the corresponding 9-bit memory cells.

When reading stored data, X and Y address signals specifying the center cell (aO) among the read memory cells are similarly input to address buffers 2b and 2a. At this time, all address decoders 3a are enabled by the R/'W signal, and in this address decoder 3a, only one line corresponding to each of the sets (9 sets) of each bit output selection line 5 is activated. be done. Therefore, the bit outputs of the memory cells corresponding to the activated bit output lines of each set are selected by the 1/25 multiplexer group 4 and become read data aO to a8.

By doing so, as shown in FIGS. 4 and 5, by accessing only one specific memory cell, it becomes possible to access other predetermined memory cells related to this at the same time.

In the above embodiment, the memory cell matrix is 5.times.5 bits, and the accessible cells are 9 bits in the pattern shown in FIG. 4.5, but the invention is not limited to this.

Effects of the Invention As described above, according to the present invention, it is possible to access a plurality of memory cells with one memory access, so that the memory contents of a group of memory cells related to each other can be processed at one time. It can be ideal for pattern processing and image processing. By converting the circuit into an LSI using a gate array or the like, the device can be made smaller.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing one example of a memory cell, FIG. 3 is a diagram showing an example of input/output bit assignment, and FIGS. 4 and 5 are memory matrices. FIG. 3 is a diagram illustrating examples of access patterns. Explanation of symbols of main parts 1...Memory matrix 3a, 3b...Address decoder 4...
・Multiplexer circuit Figure 1 Both α+C, 2 (1304CIS06070 also Figure 4

Claims (2)

[Claims] (1) A write address decoder that receives an address signal for specifying one memory cell in a memory matrix and makes it possible to write input data to other predetermined memory cells in addition to this one memory cell. means and
1. A memory control device comprising: input data supply means for supplying corresponding input data to each memory cell set in a writable state. (2) A write address decoder that receives an address signal for specifying one memory cell in the memory matrix and makes input data writable to other predetermined memory cells in addition to this one memory cell. means and
input data supply means for supplying corresponding input data to each memory cell set in a writable state; and receiving the address signal to read stored data from the one memory cell and the predetermined other memory cell. 1. A memory control device comprising: read address decoder means for enabling reading.