JPS623484B2 - - Google Patents
Info
- Publication number
- JPS623484B2 JPS623484B2 JP12758580A JP12758580A JPS623484B2 JP S623484 B2 JPS623484 B2 JP S623484B2 JP 12758580 A JP12758580 A JP 12758580A JP 12758580 A JP12758580 A JP 12758580A JP S623484 B2 JPS623484 B2 JP S623484B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- integral holding
- recording
- integral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 108010085603 SFLLRNPND Proteins 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
- G11B5/027—Analogue recording
- G11B5/035—Equalising
Description
【発明の詳細な説明】
本発明は常に最適な状態で録音できるようにし
たテープレコーダの録音回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording circuit for a tape recorder that allows recording in an optimal state at all times.
テープレコーダにおいて、原音に対してできる
だけ忠実に録音再生できるようにするため、一般
には使用するテープの種類に合せた録音条件をス
イツチで切換使用できるようにしておき、使用す
るテープ毎に条件を選択している。 In order to be able to record and play back the original sound as faithfully as possible with a tape recorder, it is generally possible to switch between recording conditions that match the type of tape being used, and select the conditions for each tape being used. are doing.
しかし市販されているテープの種類は多く、ま
た同一種類のものでも個々のテープによつて性能
のパラツキが存在するため、スイツチで切換え最
適な録音状態を得ることは困難である。 However, there are many types of tapes on the market, and even tapes of the same type have variations in performance depending on the individual tapes, so it is difficult to switch and obtain the optimum recording condition.
本発明はそこで録音しながら最適な録音状態が
得ることの出来るようにしたテープレコーダの録
音回路を提供するものである。 The present invention provides a recording circuit for a tape recorder that allows an optimum recording condition to be obtained while recording.
以下本発明を図面に従つて説明をする。1は情
報を録音するためのテープで、消去ヘツド2、録
音ヘツド3及び再生ヘツド4に順次接する。 The present invention will be explained below with reference to the drawings. Reference numeral 1 denotes a tape for recording information, which is brought into contact with an erasing head 2, a recording head 3, and a reproducing head 4 in this order.
5は前記録音ヘツド3に接続された録音回路
で、マイクロホンあるいはチユーナ等の録音信号
源6に接続された録音アンプ7、与えられる直流
信号の大きさによつて周波数特性を変化する可変
特性録音アンプ8、バイアストラツプ9及びバイ
アス発振回路10を有する。11は再生ヘツド4
に接続された再生回路で、再生プリアンプ12及
び再生アンプ13を備える。15は補償すべき周
波数信号のみを通過させる帯域フイルター16を
介して録音アンプ7に接続された第1積分保持回
路で、録音すべき録音信号を一時的に積分し保持
する。17は前記と同一の通過周波帯域を有する
帯域フイルタ18を介して再生プリアンプ12に
接続された第2積分保持回路で、前述と同様に再
生ヘツド4で再生された再生信号を積分保持す
る。Reference numeral 5 denotes a recording circuit connected to the recording head 3, a recording amplifier 7 connected to a recording signal source 6 such as a microphone or a tuner, and a variable characteristic recording amplifier whose frequency characteristics change depending on the magnitude of the applied DC signal. 8, a bias trap 9 and a bias oscillation circuit 10. 11 is playback head 4
A reproducing circuit connected to the reproducing circuit includes a reproducing preamplifier 12 and a reproducing amplifier 13. A first integral holding circuit 15 is connected to the recording amplifier 7 via a band filter 16 that passes only the frequency signal to be compensated, and temporarily integrates and holds the recording signal to be recorded. A second integral holding circuit 17 is connected to the reproduction preamplifier 12 via a band filter 18 having the same pass frequency band as described above, and integrates and holds the reproduced signal reproduced by the reproduction head 4 in the same manner as described above.
19は前記第1積分保持回路15及び第2積分
保持回路17の出力を比較する比較回路、20は
前記比較回路19の出力をゲートするゲート回
路、21,22,23は前記第1、第2積分保持
回路15,17及びゲート回路20を制御する単
安定マルチバイブレータである。24は無安定マ
ルチバイブレータで、発生されたパルス信号は、
その一部が直接第1積分保持回路15及び単安定
マルチバイブレータ21に加えられ、前記発生さ
れたパルス信号の残りは分周回路25を介して第
2積分保持回路17、単安定マルチバイブレータ
22,23に供給される。 19 is a comparison circuit that compares the outputs of the first integration holding circuit 15 and the second integration holding circuit 17; 20 is a gate circuit that gates the output of the comparison circuit 19; 21, 22, and 23 are the first and second integration holding circuits; This is a monostable multivibrator that controls the integral holding circuits 15 and 17 and the gate circuit 20. 24 is an astable multivibrator, and the generated pulse signal is
A part of it is directly applied to the first integral holding circuit 15 and the monostable multivibrator 21, and the rest of the generated pulse signal is applied to the second integral holding circuit 17, the monostable multivibrator 22, 23.
26は分周回路25のクロツク周波数を制御す
る制御回路で、フライホイール等テープ1の走行
速度に関係ある回転体の回転数を検出する回転検
出器27と、該回転検出器27で検出された信号
を矩形波信号に波形整形する波形整形回路28
と、PLL回路32とを備える。前記PLL回路32
は一方の入力に前記矩形波信号が、他方の入力に
分周器29の出力が夫々加えられる位相比較回路
30及び電圧制御発振回路31とよりなる。 26 is a control circuit that controls the clock frequency of the frequency dividing circuit 25, and a rotation detector 27 that detects the rotation speed of a rotating body such as a flywheel that is related to the running speed of the tape 1; Waveform shaping circuit 28 that shapes the signal into a rectangular wave signal
and a PLL circuit 32. The PLL circuit 32
consists of a phase comparison circuit 30 and a voltage controlled oscillation circuit 31 to which the rectangular wave signal is applied to one input and the output of the frequency divider 29 is applied to the other input, respectively.
次に本発明の動作について説明をする。録音信
号源6よりの録音信号(第2図ニ)は録音アンプ
7、可変特性録音アンプ8を介してバイアス振回
路10よりのバイアス信号とともに録音ヘツド2
に加えられ、テープ1に録音される。前記録音信
号の一部は帯域フイルター16を通つて第1積分
保持回路15に加えられ、積分され(第2図
ホ)、保持される(第2図ヘ)。 Next, the operation of the present invention will be explained. The recording signal from the recording signal source 6 (FIG. 2 D) is sent to the recording head 2 along with the bias signal from the bias oscillation circuit 10 via the recording amplifier 7 and the variable characteristic recording amplifier 8.
is added to Tape 1 and recorded on Tape 1. A part of the recording signal is applied to the first integration holding circuit 15 through the band filter 16, where it is integrated (FIG. 2(e)) and held (FIG. 2(f)).
一方テープ1に録音された信号は再生ヘツド4
で再生され、再生プリアンプ12、再生アンプ1
3で増幅されスピーカ14を駆動する。前記再生
プリアンプ12で増幅された再生信号(第2図
チ)は、帯域フイルター18でフイルターされ、
第2積分保持回路17で積分され(第2図リ)、
保持される(第2図ヌ)。 On the other hand, the signal recorded on tape 1 is sent to playback head 4.
is played back by the playback preamplifier 12 and the playback amplifier 1.
3 and drives the speaker 14. The reproduction signal (FIG. 2 H) amplified by the reproduction preamplifier 12 is filtered by a band filter 18,
It is integrated by the second integral holding circuit 17 (Fig. 2),
It is retained (Fig. 2).
そして前記第1積分保持回路15及び第2積分
保持回路17の出力を比較回路19に加え比較す
るが、前記録音信号がテープ1に録音され、再生
されるまで録音ヘツド3と再生ヘツド4のギヤツ
プ間の距離lとし、テープスピードをvとすれば
△t=l/vの時間差がある。 The outputs of the first integral holding circuit 15 and the second integral holding circuit 17 are then added to the comparing circuit 19 for comparison. If the distance between them is l and the tape speed is v, there is a time difference of Δt=l/v.
従つて録音信号を第1積分保持回路15で保持
した後、△t秒後に再生ヘツド14で再生され、
第2積分保持回路17に保持された信号と比較す
る必要がある。 Therefore, after the recording signal is held in the first integral holding circuit 15, it is played back in the playback head 14 after Δt seconds.
It is necessary to compare the signal held in the second integral holding circuit 17.
そこで無安定マルチバイブレータ24のパルス
信号(第2図ハ)の立上りで第1積分保持回路1
5を動作開始し、同時に反転された単安定マルチ
バイブレータ21の反転している間に到来する録
音信号を積分した値の最大ピーク値を保持する。 Therefore, at the rising edge of the pulse signal of the astable multivibrator 24 (Fig. 2 C), the first integral holding circuit 1
5, and at the same time, the maximum peak value of the integrated value of the recording signal that arrives while the monostable multivibrator 21 is being inverted is held.
一方第2積分保持回路17には制御回路26よ
りのクロツクパルス信号(第2図ロ)を分周回路
25で分周して得た分周パルス信号(第2図ト)
が加えられる。 On the other hand, the second integral holding circuit 17 receives a frequency-divided pulse signal (FIG. 2-T) obtained by dividing the clock pulse signal (FIG. 2-B) from the control circuit 26 by the frequency dividing circuit 25.
is added.
この分周パルス信号は無安定マルチバイブレー
タ24よりのパルス信号と立上りは一致されてお
り、且つ前記△tと同一時間になるようにされて
いるので、第2積分保持回路17も前記分周パル
ス信号の立下りで動作させれば、第2積分保持回
路17の動作開始時間が△t遅れるので、第1積
分保持回路15に保持されたのと同時刻の再生信
号が第2積分保持回路17にも保持される。 Since this frequency-divided pulse signal has the same rising edge as the pulse signal from the astable multivibrator 24 and is set to have the same time as Δt, the second integral holding circuit 17 also receives the frequency-divided pulse signal. If the operation is performed at the falling edge of the signal, the operation start time of the second integral holding circuit 17 will be delayed by Δt, so that the reproduced signal at the same time as that held in the first integral holding circuit 15 will be transferred to the second integral holding circuit 17. is also retained.
このとき分周パルス信号にて単安定マルチバイ
ブレータ22が反転され、前記と同時間内の再生
信号を積分した値の最大ピーク値を保持し、第
1、第2積分保持回路15,17に保持している
信号を比較する。単安定マルチバイブレータ22
が元に復帰されるとき、単安定マルチバイブレー
タ23が反転されゲート回路20をオンさせる。
若し比較回路19で比較される信号に差があるの
なら、比較回路19から正又は負の信号を生じ
(第2図ル)、可変特性録音アンプ8の周波数特性
を変えて補償する。 At this time, the monostable multivibrator 22 is inverted by the frequency-divided pulse signal, and the maximum peak value of the integrated value of the reproduced signal within the same time as above is held, and is held in the first and second integral holding circuits 15 and 17. Compare the signals. Monostable multivibrator 22
When is restored, the monostable multivibrator 23 is inverted, turning on the gate circuit 20.
If there is a difference between the signals compared by the comparison circuit 19, a positive or negative signal is generated from the comparison circuit 19 (see FIG. 2), and the frequency characteristics of the variable characteristic recording amplifier 8 are changed to compensate.
尚、今―周波数信号についてのみ補償する場合
について説明したが、幾つかの周波数信号にわた
つて補償したいときは、夫々補償すべき周波数に
対応した帯域フイルタ及び積分保持回路を設けて
おけばよい。 Although the case where only the frequency signal is compensated has been described, if it is desired to compensate for several frequency signals, it is sufficient to provide a band filter and an integral holding circuit corresponding to each frequency to be compensated.
前述において可変特性アンプ8の周波数特性を
補償する場合について記述したが、可変特性アン
プ8のゲインを補償することもできる。 Although the case where the frequency characteristics of the variable characteristic amplifier 8 are compensated has been described above, the gain of the variable characteristic amplifier 8 can also be compensated.
本発明のテープレコーダの録音回路は上述した
如く、第2積分保持回路の積分保持時間を第1積
分保持回路の積分保持時間より略録音ヘツドと再
生ヘツト間のテープ走行時間遅延させたので、第
2積分保持回路には第1積分保持回路に積分保持
された録音信号と同時刻の再生信号が積分保持さ
れるから、比較回路では同一の信号を比較でき
る。従つて著じるしく特性が時間と共に変化する
音楽等を録音する場合でも常に良好な状態で録音
できる。 As described above, in the recording circuit of the tape recorder of the present invention, the integral holding time of the second integral holding circuit is delayed from the integral holding time of the first integral holding circuit by approximately the tape running time between the recording head and the playback head. Since the two integral holding circuits integrate and hold the recorded signal integrated and held in the first integral holding circuit and the playback signal at the same time, the comparing circuit can compare the same signals. Therefore, even when recording music or the like whose characteristics change significantly over time, it can always be recorded in good condition.
第1図は本発明のテープレコーダの録音回路、
第2図は本発明の各部の信号波形図である。
1……テープ、3……録音ヘツド、4……再生
ヘツド、5……録音回路、8……可変特性アン
プ、11……再生回路、15……第1積分保持回
路、17……第2積分保持回路、19……比較回
路、20……ゲート回路、24……無安定マルチ
バイブレータ、25……分周回路、26……制御
回路。
FIG. 1 shows the recording circuit of the tape recorder of the present invention.
FIG. 2 is a signal waveform diagram of each part of the present invention. DESCRIPTION OF SYMBOLS 1...tape, 3...recording head, 4...playback head, 5 ...recording circuit, 8...variable characteristic amplifier, 11 ...playback circuit, 15...first integral holding circuit, 17...second Integral holding circuit, 19... Comparison circuit, 20... Gate circuit, 24... Astable multivibrator, 25... Frequency dividing circuit, 26 ... Control circuit.
Claims (1)
回路と、前記録音信号を再生ヘツドにて再生し得
た再生信号を積分保持する第2積分保持回路と、
前記第1積分保持回路の保持時間を制御するパル
ス信号を発生させるパルス信号発生回路と、第2
積分保持回路の保持時間を制御する分周信号を形
成する分周回路と、第1、第2積分保持回路に積
分保持された信号を比較する比較回路と、前記録
音信号の処理系統に接続され比較回路の出力にて
特性が補償される補償回路とよりなり、前記分周
信号にて第2積分保持回路の積分保持時刻を遅延
させ、第1積分保持回路に積分保持された録音信
号と同時刻の再生信号が第2積分保持回路に積分
保持されるようにしたことを特徴とするテープレ
コーダの録音回路。1. A first integral holding circuit that integrally holds a part of the recorded signal, and a second integral holding circuit that integrally holds a reproduced signal obtained by reproducing the recorded signal with a playback head.
a pulse signal generation circuit that generates a pulse signal that controls the holding time of the first integral holding circuit;
A frequency dividing circuit that forms a frequency divided signal that controls the holding time of the integral holding circuit, a comparison circuit that compares the signals integrally held in the first and second integral holding circuits, and a comparator circuit that is connected to the recording signal processing system. It consists of a compensation circuit whose characteristics are compensated by the output of the comparator circuit, and uses the frequency divided signal to delay the integral holding time of the second integral holding circuit, so that the recording signal is the same as the recording signal integrally held in the first integral holding circuit. 1. A recording circuit for a tape recorder, characterized in that a time playback signal is integrally held in a second integral holding circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12758580A JPS5750319A (en) | 1980-09-11 | 1980-09-11 | Sound recording circuit of tape recorder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12758580A JPS5750319A (en) | 1980-09-11 | 1980-09-11 | Sound recording circuit of tape recorder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5750319A JPS5750319A (en) | 1982-03-24 |
| JPS623484B2 true JPS623484B2 (en) | 1987-01-26 |
Family
ID=14963699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12758580A Granted JPS5750319A (en) | 1980-09-11 | 1980-09-11 | Sound recording circuit of tape recorder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5750319A (en) |
-
1980
- 1980-09-11 JP JP12758580A patent/JPS5750319A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5750319A (en) | 1982-03-24 |
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