JPS6235538A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6235538A JPS6235538A JP17405785A JP17405785A JPS6235538A JP S6235538 A JPS6235538 A JP S6235538A JP 17405785 A JP17405785 A JP 17405785A JP 17405785 A JP17405785 A JP 17405785A JP S6235538 A JPS6235538 A JP S6235538A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- layer
- high melting
- point metal
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000002844 melting Methods 0.000 claims abstract description 33
- 230000008018 melting Effects 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 21
- 239000000758 substrate Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910021332 silicide Inorganic materials 0.000 abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 42
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 239000010937 tungsten Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910001128 Sn alloy Inorganic materials 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、積層構造を有する高密度、高集積度の半導体
装置に係わり、特に上層と下層との配線層間接続の改良
をはかった半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-density, highly integrated semiconductor device having a stacked structure, and particularly to a semiconductor device with improved interconnection between upper and lower layers. .
〔発明の技術的背景とその問題点）
近年、半導体集積回路の高密度化に伴い、配線抵抗、配
線間コンタクト抵抗、配線と基板とのコンタクト抵抗等
の低減化が必要となっている。また、上層に抵抗として
半導体配線を引き回すことも、例えば抵抗負荷型メモリ
セル（スタティックＲＡＭ）のＣ−ＭＯ８回路等では重
要となっている。[Technical Background of the Invention and Problems Therewith] In recent years, with the increase in the density of semiconductor integrated circuits, it has become necessary to reduce wiring resistance, contact resistance between wirings, contact resistance between wiring and a substrate, etc. Further, it is also important to route semiconductor wiring as a resistor in the upper layer, for example, in a C-MO8 circuit of a resistive load type memory cell (static RAM).
一方、配線材料としては、熱的な安定性と電気点金属を
配線するのが効果的である。しかしながら、高融点金属
の中でシリコンとの反応温度が最も高いとされるタング
ステンさえ、７００ ［℃］以上の加熱工程を通過させ
ることにより、容易に珪化物反応が起こる。従って、第
８図（ａ）に示す如くシリコン層８１上の酸化膜８２に
開口したのため、接続孔を埋めることは極めて困難であ
る。On the other hand, as a wiring material, it is effective to use thermal stability and electrical point metal for wiring. However, even tungsten, which is said to have the highest reaction temperature with silicon among high-melting point metals, easily undergoes a silicide reaction when subjected to a heating process of 700[° C.] or higher. Therefore, as shown in FIG. 8(a), since an opening is formed in the oxide film 82 on the silicon layer 81, it is extremely difficult to fill the contact hole.
即ち、珪化物化により形成されたタングステン珪化物８
４は、シリコン［８１の中に埋没するのである。また、
珪化物化することにより、タングステンの抵抗が１桁以
上も増加する等の問題があった。That is, tungsten silicide 8 formed by silicification
4 is buried in silicon [81. Also,
There is a problem in that the resistance of tungsten increases by more than one digit due to silicification.
〔発明の目的）
本発明は上記事情を考慮してなされたもので、その目的
とするところは、上下層半導体間の配線抵抗を増大させ
ることなく、高融点金属を用いた立体配線構造を実現す
ることができ、高密度化及び高集積化に適した半導体装
置を提供することに−ある。[Object of the Invention] The present invention was made in consideration of the above circumstances, and its purpose is to realize a three-dimensional wiring structure using a high melting point metal without increasing the wiring resistance between upper and lower layer semiconductors. It is an object of the present invention to provide a semiconductor device that can be made more compact and suitable for higher density and higher integration.
本発明の母子は、高融点金属に加え高温熱処理でも安定
な高融点金属窒化物を用いることにより、高融点金属の
珪化物化を防止することにある。The main feature of the present invention is to prevent the refractory metal from becoming silicified by using a refractory metal nitride that is stable even during high-temperature heat treatment in addition to the refractory metal.
１体層を積層し、それぞれの半導体層に所定の素子を形
成した半導体装置において、上下半導体層の配ＩＩ層間
接続に高融点金属を用い、且つ該高融点金属と前記各半
導体層との接続部を高融産金、３の窒化物で形成するよ
うにしたものである。In a semiconductor device in which one layer is stacked and a predetermined element is formed in each semiconductor layer, a high melting point metal is used for the interconnection between the upper and lower semiconductor layers, and the high melting point metal is connected to each of the semiconductor layers. The first part is made of highly fertile gold and nitride of No. 3.
本発明によれば、上下層間の配線部のシリコン１と接触
する部分が高融点金属窒化物で形成されており、この金
属窒化物は金属に比して極めて安定なものであり、半導
体製造工程における熱処理（１０００℃前後）でも珪化
物化しない。このため、シリコン層と接触しない高融点
金属が珪化物化することを未然に防止できる。従って、
低抵抗立体配線を実現することができ、半導体装置の高
密度化及び高集積化に極めて有効である。According to the present invention, the portion of the wiring between the upper and lower layers that contacts the silicon 1 is formed of a high melting point metal nitride, and this metal nitride is extremely stable compared to metal. It does not turn into silicide even after heat treatment (around 1000°C). Therefore, it is possible to prevent the high melting point metal that does not come into contact with the silicon layer from turning into silicide. Therefore,
It is possible to realize low-resistance three-dimensional wiring, and it is extremely effective for increasing the density and integration of semiconductor devices.
以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
・第１図は本発明の一実施例に係わる半導体装置の要部
構成を示す断面図である。図中１１はシリコン基板で、
この基板１１の表面には拡散！１１２が選択形成されて
いる。シリコン基板１１上にはシリコン酸化摸１３を介
してシリコン偶１７が形成され、このシリコン層１７の
一部に拡散！１１１８が形成されている。そして、上記
拡散１１２゜・１８との接続に、高融点金属摸１５及び
高融点台−属窒化！１１４．１６のサンドインチ構造が
用いらｉている。なお、図には示さないが、シリコン基
、゛−板１１及びシリコン１１１７にはそれぞれ所定の
素−子が形成され、各素子の一部が拡散１’！１２．１
８にそれぞれ接続されるものとなっている。- FIG. 1 is a cross-sectional view showing the main part configuration of a semiconductor device according to an embodiment of the present invention. 11 in the figure is a silicon substrate,
Diffusion on the surface of this substrate 11! 112 is selectively formed. A silicon layer 17 is formed on the silicon substrate 11 via a silicon oxide layer 13, and is diffused into a part of this silicon layer 17! 1118 is formed. Then, in connection with the diffusion 112° 18, a high melting point metal model 15 and a high melting point base metal nitride! 114.16 sand inch structure is used. Although not shown in the figure, predetermined elements are formed on the silicon base, the plate 11, and the silicon 1117, and a portion of each element is diffused 1'! 12.1
8, respectively.
次に、上記構造の半導体装置の製造方法について説明す
る。Next, a method for manufacturing a semiconductor device having the above structure will be described.
まず、第２図（ａ）に示す如く、面方位（１００）、比
抵抗６〜８［Ωｃｔｎ ］のＰ型シリコン基板１１の表
面の所望領域に、加速電圧３゜［ＫｅＶ］で例えばＡｓ
＋を３ｘ １０” ［ｃ／ｌＩ’ ］イオン注入し、
その後９００ ［℃］、３０分の熱処理を行い、高濃度
不純物拡散層１２を形成した。First, as shown in FIG. 2(a), for example, an As
+3x 10"[c/lI'] ion implantation,
Thereafter, heat treatment was performed at 900 [° C.] for 30 minutes to form a high concentration impurity diffusion layer 12.
続いて、ＬＰＣＶＤ法で基板１１上の全面に厚さ１．５
［μｍ］のシリコン酸化膜１３を堆積し、通常のフ第１
〜リソグラフィとＲＩＥ技術により、０．７［μｍ口］
のコンタクトホール１３ａを形成した。Subsequently, the entire surface of the substrate 11 is coated with a thickness of 1.5 mm using the LPCVD method.
A silicon oxide film 13 of [μm] is deposited and
~0.7 [μm opening] using lithography and RIE technology
A contact hole 13a was formed.
次いで、スパッタリング装置を用い、窒素とアルゴンと
の混合ガス雰囲気中（圧力１ ［履ｔＯｒｒ］１４′を
形成した。Next, a sputtering device was used to form a mixed gas atmosphere of nitrogen and argon (pressure 1[tOrr] 14').
次いで、ＬＰＣＶＤ法を用いて、全面にタングステン膜
１５を被着し、ＲＩＥエッチバックで酸化ｊｌ１１３上
のタングステン膜を除去した。これにより、第２図（Ｃ
）に示す如くコンタクトホール１３ａの中にタングステ
ン膜１５が埋込み形成された。なお、上記エッチバック
は、コンタクトホール１３ａ内のタングステン膜１５の
表面がシリコン酸化１１３の表面より僅かに低くなる程
度とした。Next, a tungsten film 15 was deposited on the entire surface using the LPCVD method, and the tungsten film on the oxidized jl 113 was removed by RIE etchback. As a result, Figure 2 (C
), a tungsten film 15 was formed embedded in the contact hole 13a. The etch back was performed to such an extent that the surface of the tungsten film 15 in the contact hole 13a was slightly lower than the surface of the silicon oxide 113.
次いで、第２図（ｄ）に示す如く、コンタクトホール１
３ａ内に再びＴｉＮ合金層１６′をバイアススパッタで
埋込み、タングステン膿１５をＴｉＮ合金層１４’、１
６’で挟んだサンドイッチ構造を形成した。その後、８
００［℃］、３０分の熱処理を行い、ＴｉＮ合金層１４
’、１６’をそれぞれ化合物化した。Next, as shown in FIG. 2(d), the contact hole 1 is
3a again with a TiN alloy layer 16' by bias sputtering, and tungsten pus 15 is deposited on the TiN alloy layers 14', 1
A 6' sandwich structure was formed. After that, 8
Heat treatment was performed at 00°C for 30 minutes to form the TiN alloy layer 14.
', 16' were each converted into a compound.
次いで、全面に厚さ０．３［μｍ１のシリコン層１７を
ＬＰＣＶＤ法で被着し、前記拡散層１８を形成すべき部
分に加速電圧４０ ［ＫｅＶ］でＡＳ＋を１Ｘ１０１４
［α）１イオン注入し、さ−前記第１図に示す構造が実
現されることになる。Next, a silicon layer 17 with a thickness of 0.3 [μm1] is deposited on the entire surface by the LPCVD method, and AS+ is applied to the portion where the diffusion layer 18 is to be formed at an acceleration voltage of 40 [KeV] at 1×1014.
[α) 1 ion implantation is performed, and the structure shown in FIG. 1 is realized.
応を起こさず、比抵抗１０’［０ｃｍ ］は保たれる不
純物拡散層１２．１８）とのコンタクト特性は良好であ
り、接触抵抗は１０４［ΩＣａｂ２］であった。The contact characteristics with the impurity diffusion layer 12.18), which did not cause any reaction and maintained a specific resistance of 10' [0 cm2], were good, and the contact resistance was 104 [ΩCab2].
このように本実施例によれば、上下シリコン層の拡散層
１２．１８間の接続にタングステン躾１５をＴｉＮｇｌ
１４．１６で挟んだサンドインチ構造を用いることによ
り、タングステン摸１５の珪化物化を防止することがで
きる。さらに、ＴＡＮとシリコンとの接触抵抗も低いこ
とから、配線抵抗の低減化をはかり得る。即ち、タング
ステン等の高融点金属を用いた低抵抗の立体配線構造を
実現でき、半導体装置の高密度化及び高集積化に極めて
有効である。In this way, according to this embodiment, the tungsten layer 15 is connected between the diffusion layers 12 and 18 of the upper and lower silicon layers.
By using the sandwich structure sandwiched between 14 and 16, it is possible to prevent the tungsten sample 15 from turning into a silicide. Furthermore, since the contact resistance between TAN and silicon is low, wiring resistance can be reduced. That is, it is possible to realize a low-resistance three-dimensional wiring structure using a high-melting point metal such as tungsten, which is extremely effective for increasing the density and integration of semiconductor devices.
予め設けたコンタクトホールに対し、高融点金属°１コ
ン酸化１３３を形成し、この酸化！１１３３のコーンタ
クトホールを高融点金属窒化Ｉｔ！Ｊ３４でカバーーパ
′１
するようにしたものである。この場合、前記高融点金属
窒化膜１４の形成に対し、高融点金属窒化、３３４の形
成が容易になる。A refractory metal °1con oxide 133 is formed in the contact hole provided in advance, and this oxidation! 1133 cone tact hole with high melting point metal nitride It! It is designed to cover the J34. In this case, the formation of the high melting point metal nitride film 334 becomes easier than the formation of the high melting point metal nitride film 14.
第４図は、下層素子に対する配線層４２（金属窒化物或
いは高濃度不純物拡散シリコン膜）上に、高融点金属窒
化ｍ４４を堆積した複合配線層と、上層シリコン！ｉ１
７に形成された高１ｒ！１不純物拡散層１８とを結線す
る際に、高融点金属膜１５の埋込みと高融点金属窒化膜
１６とを配線として用いたものである。この場合、実質
的に上層と下層とは、第１図の埋込み配線構造と同様な
積層構造で接続される。FIG. 4 shows a composite wiring layer in which high melting point metal nitride m44 is deposited on a wiring layer 42 (metal nitride or high concentration impurity diffused silicon film) for lower layer elements, and an upper layer of silicon! i1
High 1r formed on 7! 1, the buried high melting point metal film 15 and the high melting point metal nitride film 16 are used as wiring when connecting the first impurity diffusion layer 18. In this case, the upper layer and the lower layer are substantially connected in a laminated structure similar to the buried wiring structure shown in FIG.
第５図は、第４図における横型配線層上にざらに低抵抗
の高融点金属膜５５を積層させ、第４図の最下層である
配線層４２を省略したものである。In FIG. 5, a high melting point metal film 55 of low resistance is roughly laminated on the horizontal wiring layer in FIG. 4, and the wiring layer 42, which is the lowest layer in FIG. 4, is omitted.
第６図は、接続すべき拡散層（配線層）１２゜１８が上
下に重なっていないとき、中間層としての高融点金属膜
を２層構造とし、一方の高融点金属膜６５を横方向に配
設して上下層の接続をとる一属模を高融点金属窒化膜で
挟んだサンドイッチ構造を用いているので、前記第１図
及び第２図に示した実施例と同様の効果が得られる。FIG. 6 shows that when the diffusion layers (wiring layers) 12°18 to be connected do not overlap vertically, the high melting point metal film 65 as an intermediate layer has a two-layer structure, and one high melting point metal film 65 is horizontally Since a sandwich structure is used in which a single layer is placed and connected between the upper and lower layers and is sandwiched between high melting point metal nitride films, the same effect as the embodiment shown in FIGS. 1 and 2 can be obtained. .
なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記積ＩＩ構造におけるシリコンと接触
する高融点金属窒化物としては、ＴｉＮ以外にＺｒＮ、
ＨｆＮでもよく、さらに上下の金属窒化物膜として異な
る金属を用いてもよい。また、中間層としての高融点金
属は、Ｗ以外にＭＯ或いはこれらの合金であってもよい
。ざらに、高融点金属膜を高融点金属窒化膜で挟んだ積
層構造の製造方法は、前記第２図に何等限定されるもの
ではなく、仕様に応じて適宜変更可能である。その他、
本発明の要旨を逸脱しない範囲で、種々変形して実施す
ることができる。Note that the present invention is not limited to the embodiments described above. For example, in addition to TiN, ZrN,
HfN may be used, and different metals may be used as the upper and lower metal nitride films. In addition to W, the high melting point metal used as the intermediate layer may be MO or an alloy thereof. In general, the method for manufacturing a laminated structure in which a high melting point metal film is sandwiched between high melting point metal nitride films is not limited to that shown in FIG. 2, and can be modified as appropriate depending on the specifications. others,
Various modifications can be made without departing from the spirit of the invention.
第１図は本発明の一実施例に係わる半導体装置るための
断面図である。
）１１・・・シリコン基板、１２．１８−・・高濃度不
純物拡散層、１３・・・シリコン酸化膜、１４．１６・
・・イ
、ＴｉＮ膜（高融点金属窒化膜）、１４’ 、１６’・
・・ＴｉＮ合金層、１５・・・タングステン膿（高融点
金属膜）、１７・・・シリコン層。
出願人 工業技術院長 等々力 達
第１図
第３図
第４図
第２ 図
第５図
第６図
第７図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. )11...Silicon substrate, 12.18-...High concentration impurity diffusion layer, 13...Silicon oxide film, 14.16-
・・TiN film (high melting point metal nitride film), 14', 16'・
...TiN alloy layer, 15...tungsten pus (high melting point metal film), 17... silicon layer. Applicant: Director of the Agency of Industrial Science and Technology Tatsu Todoroki Figure 1 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6 Figure 7
Claims (3)
導体層に所定の素子を形成した半導体装置において、上
下半導体層の配線層間接続に高融点金属を用い、且つ該
高融点金属と前記各半導体層との接続部を高融点金属の
窒化物で形成してなることを特徴とする半導体装置。(1) In a semiconductor device in which semiconductor layers are stacked via an insulating layer and a predetermined element is formed in each semiconductor layer, a high melting point metal is used for interconnection between the upper and lower semiconductor layers, and the high melting point metal and the A semiconductor device characterized in that a connection portion with each semiconductor layer is formed of a nitride of a high melting point metal.
れらの合金であり、前記接続部の高融点金属窒化物はＴ
ｉＮ、ＺｒＮ或いはＨｆＮであることを特徴とする特許
請求の範囲第１項記載の半導体装置。(2) The high melting point metal other than the connecting portion is Mo, W, or an alloy thereof, and the high melting point metal nitride in the connecting portion is T.
2. The semiconductor device according to claim 1, wherein the semiconductor device is made of iN, ZrN, or HfN.
する特許請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein each of the semiconductor layers is made of silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17405785A JPS6235538A (en) | 1985-08-09 | 1985-08-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17405785A JPS6235538A (en) | 1985-08-09 | 1985-08-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6235538A true JPS6235538A (en) | 1987-02-16 |
| JPH0422339B2 JPH0422339B2 (en) | 1992-04-16 |
Family
ID=15971863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17405785A Granted JPS6235538A (en) | 1985-08-09 | 1985-08-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6235538A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6427243A (en) * | 1987-03-30 | 1989-01-30 | Ibm | Conductive structure for semiconductor device |
| JPH01298717A (en) * | 1988-05-27 | 1989-12-01 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
-
1985
- 1985-08-09 JP JP17405785A patent/JPS6235538A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6427243A (en) * | 1987-03-30 | 1989-01-30 | Ibm | Conductive structure for semiconductor device |
| JPH01298717A (en) * | 1988-05-27 | 1989-12-01 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0422339B2 (en) | 1992-04-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |