JPS6235574A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET having the desired threshold voltage in good reproducibility by ion implanting an implanting energy which passes a gate electrode with ions of 80 or less of mass number to a substrate. CONSTITUTION:Ions of 80 or less of mass number such as implanting energy which passes 11B through a gate electrode 3 are implanted to a substrate 1 having a field effect transistor in which a threshold value is displaced to negative by desired value to set the threshold value to the desired value, and the substrate 1 is annealed at 300-450 deg.C as required. Here, in case of implanting 11B in dosage of 1.0X10<10>dose/cm<2>, if it is annealed at 380 deg.C for 5min after implanting approx. 0.3V, 11B, it can be adjusted in a direction of approx. 0.2V positive.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly a method for manufacturing a plurality of field effect transistors (hereinafter referred to as F field effect transistors) formed on a compound semiconductor substrate.
This relates to the adjustment of the threshold voltage of ET (hereinafter referred to as ET).

(Prior art) Regarding the conventional FET manufacturing method, please refer to the literature, Institute of Electronics and Communication Engineers Technical Research Report ED83-74 (November 28, 1980)
), as described in p. 9-16, etc., after implanting 1.2-ner ions for the active layer into the substrate and annealing at a temperature of around 800°C, a heat-resistant gate electrode forming a Schottky barrier is formed, Ion implantation into the i-layer formation stage 80
After annealing at a temperature of around 0° C., an ohmic electrode is formed to fabricate an FET. Also, generally FE
The threshold voltage of T is adjusted by changing the amount of donor ions implanted for the active layer.

(Problems to be Solved by the Invention) However, in semiconductor devices formed by the method described above, variations in the characteristics of current compound semiconductor substrates and variations in conditions during the manufacturing process are unavoidable. It has been difficult to form FETs with similar threshold voltages over all substrates with good reproducibility. In addition, in the FET manufacturing process, the threshold voltage of the FET can be measured after the ohmic electrode is formed, but if the FET is heated to 500°C or higher after the ohmic electrode is formed, the FET characteristics will deteriorate significantly. It was impossible to additionally implant ions and perform annealing at 500° C. or higher to adjust the threshold voltage.

Therefore, an object of the present invention is to adjust the threshold voltage of an FET by utilizing crystal defects generated by ion implantation without annealing at temperatures higher than 500°C, thereby achieving a desired threshold voltage. The objective is to provide FETs with good reproducibility.

(Means for Solving the Problems) The present invention provides a plurality of compound semiconductor substrates by forming source electrodes and drain electrodes making ohmic contact with each of a plurality of compound semiconductor substrates on which active layers are formed, and gate electrodes forming a Schottky barrier. forming a field effect transistor, measuring a threshold voltage of a predetermined field effect transistor among the field effect transistors, and having a field effect transistor whose threshold voltage deviates more negatively than a desired value; The threshold voltage is set to a desired value by implanting ions having a mass number of 80 or less with an implantation energy that passes through at least the gate electrode, and then, if necessary, the This is to anneal the substrate.

(Function) In the present invention, after forming an FET as described above, an FET whose threshold voltage deviates more negatively than a desired value is obtained by implanting ions having a mass number of 80 or less at least through the gate electrode. Since ions are implanted into the substrate, lattice defects are generated in the element region due to the ion implantation. This lattice defect makes it possible to shift the threshold voltage of the FET in the positive direction, which is negative from the target value, to obtain the target threshold voltage. In addition, by annealing at a temperature of 300°C to 450°C after this ion implantation, the point defects that are sufficiently isolated in the crystal disappear, and the value of the point defect, which represents the element characteristics of the FET, is greatly reduced. It is possible to shift the threshold voltage in the positive direction and obtain a FET with the desired threshold voltage without causing any damage.Since annealing is not performed at a temperature of 500°C or higher, there is no significant deterioration of the FET element characteristics. do not have.

(Example) FIG. 1 is a cross-sectional view of an element for explaining the present invention in detail, FIG. 2 is a diagram for explaining the relationship between ion implantation amount and threshold voltage, and FIG. The figure is a diagram for explaining the relationship between the ion implantation amount and the value. Embodiments will be described below with reference to the drawings.

As shown in FIG.
A FET is formed by sequentially forming a gate 3, a highly doped n-type conductive layer (hereinafter referred to as a layer) 4, a source electrode 5 and a drain electrode 6 making ohmic contact. Similarly, FETs are formed on other GaAs substrates (not shown). Here, W-kt gate 3 is W-At (Atl at%),
Film thickness is 1000X, gate length LG = 1.0 A
m, l"h width WG = 10 μm. Next, after measuring the threshold voltage using a probe needle, the GaAs substrate on which the FET that attempts to smooth the threshold voltage VT in the positive direction is formed is Pass B through the gate to n layer 2
The implantation is performed with an accelerating voltage of 100 keV implanted throughout.

Here, if the accelerating voltage is low, damage will be caused in a shallow position from the surface, and if it is high, damage will be caused in a deep position. Next, 380℃,
Perform annealing for 5 minutes.

Next, Figure 2 compares the case where only the B implant is repeated and the case where the process of annealing at 380°C for 5 minutes after the 11B implant is repeated, with the horizontal axis representing the ion implantation amount and the vertical axis representing the ion implantation amount. This is a diagram illustrating the difference between the threshold voltage (7) and the threshold voltage (7). 1.0 x 10 as shown in Figure 2
When only B is implanted at a dose of 7 cm2, the voltage can be adjusted to about 0.3 V, and when annealing is further performed at 380° C. for 5 minutes after B implant, it is possible to adjust the voltage to about 0.2 V in the positive direction. Still, 1 compared to the case of B injection only.
It is observed that there is less variation in the linear relationship between the ion implantation amount and the threshold voltage when annealing is performed at 380° C. for 5 minutes after 1B implantation. FIG. 3 further shows the change in value. 1B injection only. ,OX 101
When 0dose/- is used, the value is approximately 450 [μA/
v2], but when annealing is further performed at 380°C for 5 minutes, it only decreases by about 100 [μA/V].
) It is possible to positively shift the value of the threshold voltage depending on the ion implantation layer without reducing the K value, and therefore it is possible to obtain an FET with the desired threshold voltage.

Note that other methods may be used up to the formation of the FET, and in the embodiment of the present invention, the GaAs substrate 1 was used as the substrate and B was used as the impurity ions to be implanted, but the substrate may be a compound semiconductor substrate. There is no limit to the impurity ions as long as they have a mass number of 80 or less that can pass through the gate electrode, and the amount of ions to be implanted is 1.0 x 10 dose 7 so as not to increase the resistance of the current path.
It is sufficient if it is less than cm2.

(Effects of the Invention) As described above in detail, according to the present invention, even after the structure of the FET is completed, if the threshold voltage has shifted more negatively than the desired value, the threshold voltage is shifted in the positive direction. It becomes possible to take the value of Therefore, even if the threshold voltage shifts to a negative value in the process of forming an FET, according to the present invention, an FET with desired characteristics can be obtained again.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view of an element to explain the present invention in detail, and FIG. 2 is a diagram to explain the relationship between ion implantation amount and threshold voltage. , FIG. 3 is a diagram for explaining the relationship between the ion implantation amount and the value. 1--GaAs substrate, 2-n layer, 3-W-At gate, 4...11 layers, 5...source electrode, 6...drain electrode Patent applicant: Oki Electric Industry Co., Ltd. Showa, month, day

Claims (2)

[Claims] (1) forming a plurality of field effect transistors by forming source and drain electrodes that make ohmic contact with each of the plurality of compound semiconductor substrates on which active layers are formed, and a gate electrode that forms a Schottky barrier; The threshold voltage of a predetermined field effect transistor among the field effect transistors is measured, and ions having a mass number of 80 or less are applied to the substrate having a field effect transistor whose threshold voltage deviates more negatively than a desired value. A method of manufacturing a semiconductor device, comprising the step of implanting ions with an implantation energy that passes through at least the gate electrode to set a threshold voltage to a desired value. (2) forming a plurality of field effect transistors by forming a source electrode and a drain electrode making ohmic contact with each of the plurality of compound semiconductor substrates on which the active layer is formed, and a gate electrode forming a Schottky barrier; The threshold voltage of a predetermined field effect transistor among the field effect transistors is measured, and ions having a mass number of 80 or less are applied to the substrate having a field effect transistor whose threshold voltage deviates more negatively than a desired value. ion implantation with an implantation energy that passes through at least the gate electrode to achieve a threshold voltage of a desired value, and then annealing the substrate at a temperature of 300° C. to 450° C. A method for manufacturing a semiconductor device, characterized by: