JPS6235942A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To perform the processing at a high speed by selecting and executing one of plural arithmetic logic instructions set to an instruction register in accordance with status information of a selected status register. CONSTITUTION:When an instruction is set from an instruction memory 1 to an instruction register 5, the contents of a status register 11 where the state of the arithmetic logic result of the instruction executed in the preceding step is held are selected by a condition selecting selector 13 in accordance with an ALU condition part 5b. The first ALU function designating part 5c or the second ALU function designating part 5d is selected by a function selecting selector 7 in accordance with this selected status information to determined a logical arithmetic function which an ALU 9 executes. Since jump to another processing is unnecessary when the processing is different by contents of status information, the processing is performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic processing device that improves processing efficiency.

[Technical background of the invention and its problems 1 In image processing, measured image data is compared with threshold data and binarized, but this processing is performed using a microprogram control method, and conventionally, This is performed by an arithmetic processing device as shown in FIG. In FIG. 3, microprograms are stored in advance in an instruction memory 1, and are sequentially read out from the instruction memory 1 according to addresses from a sequencer 3 and set in an instruction register 25.

The instruction register 25 usually consists of several tens of bits, including a jump control section 25a1, an arithmetic logic function specification section,
That is, the ALU function designation section 25b, the R selection section 25C, the S selection section 25 (1), and the image memory read command, image memory address control (
Increment, Increment 1~, etc.). The ALU function specifying section 25b of the instruction register 25 is an arithmetic logic unit, that is, an
It is connected to L U 9, and the arithmetic unit l! of A L U 9 is connected to L U 9.
l! Functions, namely + (addition), - (subtraction), AND
(logical product), OR (logical sum), l-11 (high level: hexadecimal FF'), LO (low level: ○), etc., is specified. The ALU 9 executes the deductive logic function specified by the ALU function specifying section 25b as described above with respect to the two inputs supplied from the S input and the R input. The S input of the ALU 9 is connected to the S select section 2 by gated by the selector 17 in the S select section 1 to section 25d of the instruction register 25.
5d is supplied from the input bus 17a, and similarly, the selector 17 is connected to the R input of the ALU 9 by the R select section 25c of the instruction register 25.
As a result, the data specified by the R select section 25c is supplied from the input bus 19a. The result of the arithmetic processing in the ALU 9 is output from the output Y of the Δl-U 9 to the output bus 9a, but there is a carry that occurs in the result of the arithmetic processing, that is, a carry, and the content of the arithmetic result is zero. Status display information such as zero indicating , overflow, etc. is held in the status register 11 from the ALU 9 . The output of the status register 11 is connected to the selector 15, and the jump control section 25a of the instruction register 25 is connected to the selector 15.
5 and is also connected to the sequencer 3.

Figure 4 shows the binarization process of image data using this conventional arithmetic processing device, i.e., when the image data is larger than the threshold data)'I (high level - hexadecimal FF) output, and if it is small, output ]-〇(low level-O
) is shown as an example of a microprogram that performs the process of outputting the image to the image memory. The operation will be briefly explained with reference to FIGS. 3 and 4.

In step 1 in FIG. 4, the image data of the image memory VRAM is set in R select]~, the threshold information is set in S select, and the calculation of Y=R-8 is performed in ALU9, that is, the data of the image memory VRAM. The threshold value is subtracted from , and in step 2, 1tr(
High level - FF in hexadecimal) is written to the image memory.

At this time, if the carry is "0" as a result of the calculation in step 1, that is, if the data threshold value of the image memory VRAM≧O, the next step 3 is skipped and the process jumps to step 4. However, as a result of the calculation in step 1, if the carry is not rOJ, that is, the data threshold value of the image memory VRAM is <0
In this case, proceed to the next step 3 and set LO (low level -
O) is stored in the image memory and the process proceeds to step 4. In step 4, the address of the image memory is incremented, the threshold value is subtracted from the data in the image memory VRAM in the same way as in step 1, and then the process jumps to step 2. -Repeat the process of 4.

Note that in the binarization process of image data, when the data in the image memory is 256×256, the process of step 2-4 is repeated 256×256 times.

In the conventional image processing arithmetic processing device configured and operated as described above, two steps, Steps 2 and 3, are performed to write -II or +-0 to the image memory depending on whether the carry is rOJ or not. In addition, if the carry is rOJ, it jumps to step 4 without executing step 3, but if the carry is not "O", it executes step 3 and then proceeds to step 4, so the carry is The number of steps to be executed differs depending on whether it is rOJ or not. In this way, in conventional processing steps, when the next process is determined by the result of a certain operation, instructions are provided for each branch so that each process can be performed using a jump instruction. Therefore, since two or more instruction steps are required, the program steps become long and high speed cannot be achieved.The number of execution steps varies depending on the data, so other processing functions (e.g. There is a problem in that synchronous parallel processing with spatial filtering processors, etc.) is difficult.

[Object of the Invention] The present invention has been made in view of the above, and its purpose is to provide an arithmetic processing device that achieves high speed and facilitates synchronized parallel processing with the processing function of a conventional processor. It's about doing.

[Summary of the Invention] In order to achieve the above object, the present invention provides an instruction register in which an instruction having a plurality of arithmetic logic instructions and a condition setting code for selecting an arithmetic logic instruction is stored in an instruction register in which an instruction in a previous step is stored. a state register that holds state information of an arithmetic logic result according to an executed result; and a condition setting code for selecting an arithmetic logic instruction of an instruction set in the instruction register to select the state information held in the state register; The gist includes a selector that selects any one of a plurality of arithmetic and logic instructions to be sent to the cell 1 in the instruction register according to the state information, and an arithmetic and logic unit that executes the arithmetic and logic instruction selected by the selector. shall be.

[Embodiments of the invention] Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of the case where the arithmetic processing device according to an embodiment of the present invention is applied to both (g?!U raccoon dogs). It compares the data and converts it into a binary value, and is controlled by a microprogram control method stored in the instruction memory 1. Each instruction stored in the instruction memory 1 is assigned an address from the sequencer 3. The instruction register 5 is sequentially read out and stored in the instruction register 5.The instruction register 5 is read out sequentially by the jump control unit 5.
a, arithmetic logic instruction selection condition setting code section, that is, A
ll, l conditioner 932 section 5b, first and second two arithmetic logic function specifying sections, namely, first AI-(J function specifying section 5c, second A L tJ function specifying section 5d1R select section 5e, S select 1~
It is comprised of a section 5f, an output direct section 5Ql, and an image memory read instruction, image memory address control (increment, decrement 1, etc.), and the like. The first ΔLtJ function specification section 5C and the second A LJ function specification section 5d of the instruction register 5 are respectively connected to the first ΔLtJ function specification section 5C of the function selection selector 7.
and second inputs D1 and D2. The output DY of the condition selection selector 13 is connected to the selection power S of the function selection selector 7, and this output signal causes the first or second input D1 or D of the function selection selector 7 to be connected.
Either the first ALU function specifying section 5C or the second ALU function specifying section 5d supplied to the ALU function specifying section 2 is selected, and the arithmetic logic function specifying signal from the selected ALU function specifying section is The output DY of the function selection selector 7 is supplied to the function selection input of the AI-U 9. ALtJ9 is
In this way, the arithmetic logic function is executed in accordance with the arithmetic logic function designation signal supplied via the function selection selector 7.

The arithmetic and logic functions executed by ALU9 are + (addition), - (subtraction), AND (logical product),
There are OR (logical sum'), l-(T (high level: hexadecimal FF), 10 (low level 20), etc.A1-U9
executes the specified arithmetic logic function supplied via the function selection selector 7 as described above with respect to the two inputs supplied from the S input and the R input. The S select section 5f of the instruction register 5 is connected to the S input of the AI U9.
When the selector 17 is set to the gate 1, the data specified by the S select section 5f is supplied from the input bus 17a, and similarly, the R input of the 8LtJ9 is set to the selector 17 by the R select l to section 5e of the instruction register 5. is gated, so that the data designated by the R select section 5e is supplied from the input bus 19a.

The result of arithmetic processing in AILLJ9 is ALLJ9
is output to the output bus 9a from the output Y of the arithmetic operation, but the carry signal generated from the ALIJ9 as a result of the arithmetic processing, that is, the carry signal, the zero signal indicating that the content of the arithmetic result is zero, or the overflow signal, etc. Such a status display signal is held in the status register 11 from the ALU 9. The status display signal held in the status register 11 is supplied to the sequencer selector 15 and then to the condition selection selector 13, where the ALU condition section 5b of the next instruction set in the instruction register 5 is sent. One of the status display signals is selected by , and this selected status display signal, that is, a carry signal, a zero signal, an overflow signal, etc., is supplied to the function selection selector 7, and the next one is selected depending on the content of this status display signal. The first ALU function specification part 5C or the second AL of the instruction
The U function designation section 5d is selected by the function selection selector 7, and as a result, the arithmetic logic function of the next instruction to be executed by the ALU 9 is determined. Further, the jump control section 5a of the instruction register 5 is connected to the sequencer 3 and the sequencer selector 15.
is supplied to perform jump control.

Next, the operation of the image processing arithmetic processing device shown in FIG. 1 will be explained with reference to a program example shown in FIG.

FIG. 2 shows an example of a program for binarizing image data by comparing it with threshold data, and these programs are stored in the instruction memory 1. When the step 1 instruction is first set from the instruction memory 1 to the instruction 1 to action registers 5 by addressing from the sequencer 3, the R select section 5e of the instruction register 5
The image data from the image memory VRAM set to 1 is supplied to the S input of the ALU 9 via the selector 17, and the threshold data set to the S select section 5f is supplied via the selector 17 to the S input of the ALU 9. Supplied to the R input of ALU9. Ince 1~action register 5 A L
Since the U function specifying unit 5C95d specifies Y=R-8 as the arithmetic logic function to be executed by the ALU 9, in step 1, the operation of subtracting the threshold data from the image data from the image memory VRAM is executed, Status information such as carry in this operation is held in the status register 11.

In the next step 2, instruction register 5
Since the condition setting code to select the carry signal is set in the ALU condition section 5b of the instruction set to , the condition selection selector 13
selects the carry signal held in the status register 11 in the previous step, and supplies this carry signal to the selection input of the function selection selector 7. As a result, the function selection selector 7 selects the first ALU function specifying section 5C when the carry signal is "0", and as a result, in the ALU 9, Y=I-IT (FF in hexadecimal
) is executed to output a high level signal, and when the carry signal is "1", the second ALLI function specification section 5d is selected, and as a result, in the ALU 9, Y=L.
Execute O and output a low level signal. This execution result is the image memory VRA selected by the output select 5g.
It is stored in M.

Next, the process advances to step 3, where the address of the image memory is incremented by 1, and the same process as in step 1, that is, the calculation of subtracting the threshold value data from the image data from the image memory VRAM, is executed, and under the control of the sequencer 3. Jumps to step 2 and loop control is performed. Thereafter, the operations of steps 2 and 3 are repeated, for example, 256×256 times for the image data in the image memory VRAM. The number of repetition steps in this case is 2 x 256 x 256 steps, which is constant regardless of the content of the data in the image memory, and the number of steps does not increase when the carry signal is not rOJ, as in the past, and the speed is increased. There is.

[Effects of the Invention] As explained above, according to the present invention, an instruction having a plurality of arithmetic logic instructions and a condition setting code for arithmetic logic instruction selection is set in the instruction register, and the instruction executed in the previous step is set. The contents of the status register holding the state of the arithmetic logic function are selected by the arithmetic logic instruction selection condition setting code, and one of the plurality of arithmetic logic instructions is selected based on the selected state information. The specified arithmetic and logic instructions are executed. As a result, when executing different processes depending on the contents of the state information, for example, when the state information is in the first state, the first instruction among the plurality of arithmetic and logic instructions is executed, without jumping to another process, In the case of the second state, there is no need to jump to anything else such as executing the second instruction, so the number of steps is shortened by the amount of jumping and executing the instruction at the location of the count, achieving speedup. In addition, the number of steps does not differ depending on the content of the state information, so it is easy to synchronize with other parallel processors, such as those for spatial filter multiplication, and as a result, processing efficiency can be improved. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic processing device without showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a program for binarizing image data executed by the device shown in FIG. 1, and FIG. 4 is a block diagram of a conventional arithmetic processing device, and FIG. 4 is a diagram showing an example of a conventional program for binarizing image data executed by the device shown in FIG. 1... Input 1 to action memory 3... Theta turn → step 5... Instruction 1 register 7... Function selection selector 9... ΔIU 11... Status register 13... Condition selection selector for

Claims (1)

[Claims] an instruction register in which an instruction having a plurality of arithmetic logic instructions and an arithmetic logic instruction selection condition setting code is set; a status register that holds state information of the arithmetic logic result as a result of executing the instruction of the previous step; The state information held in the state register is selected by the arithmetic logic instruction selection condition setting code of the instruction set in the instruction register, and the plurality of arithmetic logics set in the instruction register are selected based on the state information. An arithmetic processing device comprising: a selector that selects one of the instructions; and an arithmetic logic unit that executes the arithmetic logic instruction selected by the selector.