JPS6236301Y2 - - Google Patents
Info
- Publication number
- JPS6236301Y2 JPS6236301Y2 JP15392981U JP15392981U JPS6236301Y2 JP S6236301 Y2 JPS6236301 Y2 JP S6236301Y2 JP 15392981 U JP15392981 U JP 15392981U JP 15392981 U JP15392981 U JP 15392981U JP S6236301 Y2 JPS6236301 Y2 JP S6236301Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- lead
- leads
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本案は半導体素子を収容するパツケージの改良
に関するものである。[Detailed Description of the Invention] The present invention relates to an improvement of a package that houses a semiconductor device.
集積回路(IC,LSIなど)を構成する半導体素
子を収容し、該半導体素子の各電極に接続し、導
出するための複数のリードを備えたパツケージP
としては、第1図にて例示したように電気絶縁性
を有するセラミツク体Cのほぼ中央部に形成した
キヤビテイF中に半導体素子Sを収容し、該半導
体素子Sの電極と接続し導出する外部リードLを
セラミツク体Cの両サイドに配置した構造のもの
が多く使用されている。 A package P that houses a semiconductor element constituting an integrated circuit (IC, LSI, etc.) and is equipped with a plurality of leads for connecting and leading out each electrode of the semiconductor element.
As illustrated in FIG. 1, a semiconductor element S is housed in a cavity F formed approximately at the center of a ceramic body C having electrical insulation properties, and an external A structure in which the leads L are arranged on both sides of the ceramic body C is often used.
このようにセラミツク体Cの両サイドにロー接
けして取付けられた複数個の外部リードLは、半
導体装置として完成し、通電検査を受けるに至る
までは各々が連接リードTにより接ながつた状態
にあり、しかる後X−X線近傍にて切断されて初
めて外部リードLとして独立し、半導体装置とし
て機能する。このように外部リードLと、これら
を接なぐ連接リードTからなるリードフレームは
一枚の金属板を所定の金型で打抜き一体成形した
ものが用いられている。 The plurality of external leads L, which are attached by soldering to both sides of the ceramic body C in this way, are connected to each other by the connecting leads T until the semiconductor device is completed and subjected to a conduction test. After that, it becomes independent as an external lead L and functions as a semiconductor device only after it is cut near the X--X line. As described above, the lead frame consisting of the external leads L and the connecting leads T connecting these leads is formed by stamping and integrally molding a single metal plate using a predetermined mold.
このようなパツケージを用いIC,LSIなど半導
体装置としての製作過程において、各々の外部リ
ードLが通電検査を受けるまで連接リードTで一
体的に接ながつた状態のままにおく理由として
は、個々の外部リードLを一個ずつ所定の位置、
間隔でロー接けするのは非常に面倒で能率が悪
い。ところが、外部リードLが所定の間隔で正確
に配置されたリードフレームをもつてすれば一度
に数多くの外部リードLのロー接けが可能となる
こと、パツケージの製作工程時における外部リー
ドL、キヤビテイFの底面等に表面処理としての
ニツケルメツキや金メツキを施す場合すべての被
メツキ部分が電気的に接ながつていると一個所だ
けに通電々極を接続すればよいこと、またパツケ
ージの運搬移送時やパツケージに半導体素子Sを
収容し、結線するなど半導体装置としての製造工
程時に各外部リードLの間隔が狂つたり、曲がる
などの不都合が発生しにくいことが主な理由であ
る。 In the process of manufacturing semiconductor devices such as ICs and LSIs using such packages, there are several reasons why each external lead L is left integrally connected with the connecting lead T until it undergoes a conduction test. Place the external leads L one by one in the specified position,
It is very troublesome and inefficient to make row joints at intervals. However, if the external leads L are attached to a lead frame in which they are accurately arranged at predetermined intervals, it becomes possible to connect many external leads L at once, and it is possible to connect the external leads L and cavity F during the package manufacturing process. When applying nickel plating or gold plating as a surface treatment to the bottom of the package, it is important to note that if all the plated parts are electrically connected, you only need to connect the current-carrying terminal to one place, and when transporting the package. The main reason is that inconveniences such as the spacing of the external leads L being out of alignment or bending are less likely to occur during the manufacturing process of the semiconductor device, such as housing the semiconductor element S in a package and connecting the wires.
ところが、このように外部リードLと連接リー
ドTを一体的に形成したリードフレームにおい
て、パツケージの製作工程の際、ロー接けの位置
決めを容易にするなどの目的で設けてある連接リ
ードTを延長した部分である延端部Taの端面が
下面Tbに対して通常直角に切断された形状にな
つていることから、半導体装置として自動組立ラ
インによる製作工程のもとで上記延端部Taの下
端が直角に切断されてできる角部Tcが組立ライ
ンの一部に引掛つたり角が立つなどして流れ移動
が円滑にいかないといつた事態が発生していた。
特に最近ではほとんど全工程が自動化されたり、
製造時の流れが速いことなどにより、わずかの角
部があつても悪影響を受けやすく、組立ラインが
停止したり、場合によつてはライン流れの不良に
もとづいて製品不良に至る事態を招く恐れもあつ
た。 However, in a lead frame in which the external lead L and the connecting lead T are integrally formed in this way, the connecting lead T, which is provided for the purpose of facilitating the positioning of brazing joints, is extended during the package manufacturing process. Since the end surface of the extended end portion Ta, which is the cut portion, is usually cut at right angles to the lower surface Tb, the lower end of the extended end portion Ta is normally cut at right angles to the lower surface Tb. The corner Tc, which is created by cutting the material at a right angle, gets caught on a part of the assembly line or has a sharp corner, which prevents smooth flow movement.
Especially recently, almost all processes have been automated,
Due to the fast-moving flow during manufacturing, even the slightest corner can be adversely affected, leading to assembly line stoppages or, in some cases, product defects due to line flow defects. It was hot too.
本案は上記に鑑みて、組立ライン等におけるリ
ードフレームの引掛かりや流れ不良による不都合
が発生しないような形状のリードフレームを備え
た半導体素子用パツケージを提供せんとするもの
である。 In view of the above, the present invention aims to provide a package for semiconductor devices having a lead frame shaped so that problems such as lead frames getting caught or poor flow do not occur on an assembly line or the like.
図により本案実施例を具体的に詳述すれば、第
2図イ,ロは第1図におけるリードフレームのみ
の部分拡大図で、これら本案実施例では連接リー
ドTの延長して成る部分(第1図における延端部
Taに相当)の下端のコーナー部分あるいは延端
部Taを持たない場合における下端のコーナー部
分に丸味をもたせた円形部Mが形成してある。こ
の円形部Mとしては、丸味があまり小さい場合に
は角ばつた直角近いものとなり、本考案所期の目
的を達成するほどの顕著な効果がなかつた。すな
わち円形部Mが0.1R以下では移動に際して円滑
性を十分もたらさないことが実験により判明し
た。この実験方法としては自動組立ラインに模し
た一定表面状態をもち、20゜の傾斜台(スベリ
台)からコーナー部に種々の丸味を形成したリー
ドフレームを備えたパツケージの各々の滑走降下
させたところ、円形部Mの丸味が0.1R以上の場
合は大差なくほぼ同等で比較的良好な滑走特性を
有するという結果が得られた。 To explain the embodiments of the present invention in detail with reference to the drawings, FIGS. 2A and 2B are partially enlarged views of only the lead frame in FIG. Extended end in Figure 1
A rounded circular portion M is formed at the lower end corner portion (corresponding to Ta) or at the lower end corner portion in the case where the extended end portion Ta is not provided. If the roundness of the circular portion M is too small, it becomes angular and nearly right-angled, and does not have a significant effect to achieve the intended purpose of the present invention. In other words, it has been found through experiments that if the circular portion M is less than 0.1R, sufficient smoothness during movement is not achieved. The experimental method involved sliding down each package cage with a lead frame with various rounded corners from a 20° slope with a constant surface condition similar to an automatic assembly line. When the roundness of the circular portion M is 0.1R or more, the results show that there is no significant difference, and the sliding properties are almost the same and relatively good.
もつとも、かかる実験は傾斜台を用いた滑走降
下させるだけのものであつて、実際の半導体装置
を製造する組立ライン等における流れ移動条件と
同等のものではないが、リードフレームの少くと
もコーナー部に丸味をもたせたことによつてパツ
ケージの流れ移動特性大巾に向上することが確認
された。なお、本考案の適用は第1図に示した如
きタイプのパツケージだけでなく、リードフレー
ムをガラス溶着するようにしたサーデイツプタイ
プのもの、あるいはリードフレームを合成樹脂で
モールドした型式のパツケージにおいてもそのま
ま適用できることは言うまでもない。 However, such an experiment merely involves sliding down a slope, and is not equivalent to the flow movement conditions on an assembly line for manufacturing actual semiconductor devices. It was confirmed that the flow movement characteristics of the package were greatly improved by giving it a rounded shape. The present invention can be applied not only to the type of package shown in Figure 1, but also to dip-type packages in which the lead frame is welded to glass, or packages in which the lead frame is molded with synthetic resin. Needless to say, it can also be applied as is.
以上のように本案半導体素子用パツケージによ
れば、半導体装置として完成に至る末だ外部リー
ドが独立してない連接リードが一体となつた状態
におけるコーナー部分に丸味が形成してあること
によつて半導体装置の自動組立ライン等での円滑
な流れ移動を達成することができ、そのため生産
性の向上と併せて品質の安定した半導体装置を製
造することができるなど多くの効果を有する。 As described above, according to the semiconductor device package of the present invention, when the semiconductor device is completed, the external leads are not independent, but the corner portions are rounded when the connecting leads are integrated. It is possible to achieve smooth flow movement on an automatic assembly line for semiconductor devices, etc., which has many effects such as improved productivity and the ability to manufacture semiconductor devices with stable quality.
第1図は従来の半導体素子用パツケージを示す
斜視図、第2図イ,ロは本案実施例による半導体
素子用パツケージを構成するリードフレームのみ
の部分拡大図である。
P……パツケージ、L……外部リード、T……
連接リード。
FIG. 1 is a perspective view showing a conventional package for semiconductor devices, and FIGS. 2A and 2B are partially enlarged views of only the lead frame constituting the package for semiconductor devices according to an embodiment of the present invention. P...Package, L...External lead, T...
Articulating lead.
Claims (1)
続される複数個の外部リードを装備した半導体素
子用パツケージにおいて、前記外部リードを接ぐ
べく一体的に形成した連接リードを有するリード
フレームの端部のコーナー部分に0.1R以上の丸
味を形成したことを特徴とする半導体素子用パツ
ケージ。 In a semiconductor device package that houses a semiconductor device and is equipped with a plurality of external leads connected to the electrodes of the semiconductor device, the end portion of a lead frame has a connecting lead integrally formed to connect the external leads. A package for semiconductor devices characterized by rounded corners of 0.1R or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15392981U JPS5858355U (en) | 1981-10-15 | 1981-10-15 | Package for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15392981U JPS5858355U (en) | 1981-10-15 | 1981-10-15 | Package for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5858355U JPS5858355U (en) | 1983-04-20 |
| JPS6236301Y2 true JPS6236301Y2 (en) | 1987-09-16 |
Family
ID=29946531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15392981U Granted JPS5858355U (en) | 1981-10-15 | 1981-10-15 | Package for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858355U (en) |
-
1981
- 1981-10-15 JP JP15392981U patent/JPS5858355U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5858355U (en) | 1983-04-20 |
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